ISL62386 Datasheet, PDF (15/20 Pages) Intersil Corporation – High-Efficiency, Quad Output System Power Supply Controller for Notebook Computers

ISL62386
flows out of the ISEN1 pin, generating a voltage drop on the
R_O resistor, which should be chosen to have the same
resistance as R_OCSET. When PGOOD pin goes high, the
ISEN1 pin current source will be removed.
When an OCP fault is detected in one SMPS channel, the
PGOOD pin will pull down to 32Ω. The ISL62386 turns the
faulted channel UGATE and LGATE off and latches off the
faulted channel.
The fault will remain latched until either of the EN pins has
been pulled below the falling EN threshold voltage, or until
V_IN has decayed below the falling POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
V_OCSET1–V_ISEN1 = I_L • R_SENSE – 10μA • R_OCSET
(EQ. 11)
Furthermore, Equation 9 is changed in Equation 12:
R_OCSET
=
I_{--O-----C-----}•_--R_{-----S----E----N----S----E--}
10 μ A
(EQ. 12)
Where R_SENSE is the series power resistor for sensing
inductor current. For example, with an R_SENSE = 1mΩ and
an OCP target of 10A, R_OCSET = 1kΩ.
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The rising overvoltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
If an OVP is detected in one SMPS channel, the PGOOD pin
will pull-down to 32Ω, and the LGATE gate-driver will turn on
the low-side MOSFET to discharge the output voltage, thus
protecting the load from potentially damaging voltage levels.
Once the FB pin voltage falls to 106% of the reference
voltage, or 1.06*0.6V = 0.636V, the faulted channel will
resume the normal switching, and PGOOD will go high when
the output voltage is in regulation. This process repeats as
long as the OVP fault is present.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2µs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V.
If a UVP fault is detected in one SMPS channel, the PGOOD
pin will pull-down to 32Ω. The ISL62386 turns the faulted
channel UGATE and LGATE off and latches off the faulted
channel.
The fault will remain latched until either of the EN pins has
been pulled below the falling EN threshold voltage, or until
VIN has decayed below the falling POR threshold.
Programming the Output Voltage
When the converter is in regulation there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
V_OUT
=
V_REF
•
⎛
⎜1
⎝
+
R^-----_B^--R--_O^---T-_T^--O--_T^---P-_O^----_M^---_{⎠⎟⎞}
(EQ. 13)
Where:
- V_OUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the V_REF (0.6V)
- R_TOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R_BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose R_TOP first when compensating the control loop, and
then calculate R_BOTTOM according to Equation 14:
R_BOTTOM
=
--^V----^R----^E----^F----^•---^R----^T----^O-----^P---
V_OUT – V_REF
(EQ. 14)
Compensation Design
Figure 27 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C_INT is a 100pF capacitor
integrated inside the IC that connects across the FB pin and the
COMP signal. R_TOP, R_FB, C_FB and C_INT form the Type-II
compensator. The frequency domain transfer function is given
by Equation15:
G_COMP(s)
=
-----------¹-----+-----^s----^•--⁽---^R----^T----^O-----^P-----+----^R-----^F----^B----⁾--^•---^C-----^F---^B-------------
s • R_TOP • C_INT • (1 + s • R_FB • C_FB)
(EQ. 15)
C_INT = 100pF
R_FB
C_FB
R_TOP
-
VO
FB
COMP
EA
+
R_BOTTOM
REF
ISL62386
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
15
FN6831.0
February 4, 2009