ISL55112 Datasheet, PDF (18/20 Pages) Intersil Corporation – High-Speed Dual Precision CCD Driver

ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, R_OIC = 68kΩ, C_L= 300pF for
H1/2OUT, C_L = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
3.4
3.3
3.2
3.1
H1 t_r
3.0
2.9
H1 t_f
2.8
2.7
2.6
2.5
2.4
-40
-20
0
20
40
60
80
PACKAGE TEMP (°C)
FIGURE 29. H1 t_r / t_f vs TEMPERATURE
Die Characteristics
SUBSTRATE AND TQFN THERMAL PAD
POTENTIAL (POWERED UP):
VSUB
TRANSISTOR COUNT:
3900
PROCESS:
SUB MICRON CMOS
TQFN Package Discussion
Typically, power dissipation is a limiting factor in CCD
array driving applications. The key tool in removing heat
from the drivers is the thermal pad on the bottom of the
TQFN package.
Electrically, this exposed pad is connected to the device
substrate and is the most negative voltage. In
applications where negative drive rails are used, this pad
must be isolated from ground and connected to the
negative bus. However, the size of the thermal pad and
the associated voltage plane/layer it connects to
determines the heat dissipation capability of the pad.
TOP VIEW
BOTTOM VIEW
The TQFN Thermal Pad is the main tool for dealing
with Power Dissipation.
FIGURE 30. ISL55112 TQFN PAD LAYOUT EXAMPLE
TOP AND BOTTOM VIEWS
The footprint for the ISL55112 should include a “Thermal
Via Array” of through-holes. Hole size and spacing of
these vias should maximize heat transfer to the bottom
of the board and away from the device. Hole size should
accommodate solder wicking requirements. The quantity
of vias is limited by pad size and recommended spacing.
Vias should also have a solid connection to the associated
power plane.
Another item that affects thermal transfer is the layout
on the bottom of the board. Circuit lands that run parallel
with the package can actually become heat barriers. If
signals are routed on the bottom, try to route signal
paths (90°) away from the pad area. Make the exposed
pad area as large as possible on the bottom layer.
(Remember in negative voltage applications the pad
needs to be electrically isolated from the ground plane.)
Reference Intersil TB-389 A grid of 1.0mm to 1.2mm
pitch thermal vias, which drop down and connect to
buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to
0.33mm in diameter, with the barrel plated to about 1.0
ounce copper. Although adding more vias (such as by
decreasing via pitch) will improve thermal performance,
diminishing returns will be seen as more and more vias
are added. Therefore, simply use as many vias as
practical for the thermal land size and your board design
ground rules.
Recommended Land Pattern (TQFN PCB
Footprint)
Please refer to the Package Outline Drawing for
recommended land size guidelines.
18
FN6649.0
September 23, 2009