ISL55112 Datasheet, PDF (11/20 Pages) Intersil Corporation – High-Speed Dual Precision CCD Driver

ISL55112
power inputs have settled but should not be allowed to
float during power-up and power-down operations.
Note: If V_SUB floats high when V_DD is applied, a 10k to
50k Resistor should be added from V_SUB to ground. For
proper power up biasing, V_SUB should not be allowed to
float high when only V_DD is applied.
Power Supply Bypassing and Printed Circuit
Board Layout
Maximum current occurs during edge-transition of the
driver outputs. Decoupling of the VP and VN rails for the
drivers is of paramount concern. This being especially
true of the high current drivers. Minimum possible lead
length from the VP/VN device connections to the
associated decoupling capacitors is key to device
performance.
Given transition times are the point of maximum current,
series inductance from the decoupling point to the VP/
VN connections and from the VOUT connection to the
CCD should be kept to the minimum possible values.
Note: The ISL55112 employs multiple bond wires on all
driver rail and driver output connections. Multiple bond
wires help reduce the device package internal bond wire
connection inductance.
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible, and the power
supply pins must be well bypassed to reduce the risk of
oscillation.
The “Evaluation Board” drawing depicts a conceptual
decoupling scenario. Capacitor values, placement and
quantities are subject to specific application
requirements. The key to decoupling, especially during
edge transitions, is to reduce the series inductance of the
VP/VN supply rails.
Decoupling Discussion and
Evaluation Board Information
• With split supply driver voltages, each VN and VP pin
should have a separate 0.1µF capacitor to ground.
The capacitors should be on the top layer of the PCB
to a ground plane. This avoids the operative
decoupling point having a via in series with the
device pin.
• Single supply applications require fewer decoupling
capacitors (VN rails are connected to ground. In this
case, the top layer should also be a ground plane
and VP pins should be decoupled as closely as
possible.
• In both cases, the return path series inductance
needs to be considered. The return current path of
the load and the decoupled point should be as close
as possible. Avoid/reduce Vias between driver rail
decoupling points and driver output to load.
Figure 5 shows the top decoupling provides the high
frequency driver rail decoupling during edge transitions
(C1, C4, C6, C11). Figure 6 shows vias between bottom
decoupling and the device pins on top increase series
inductance. However, bottom decoupling replenishes the
top decoupling before and after edge currents occur.
Additional bulk decoupling (22µF to 4.7µF) should also be
used. This is low frequency decoupling and need not be
located as close to the output area of the device.
FIGURE 5. TOP COMPONENT AND PCB ARTWORK
FIGURE 6. BOTTOM COMPONENT AND PCB ARTWORK
Output Impedance Control (OIC)
An external Resistor, R_OIC, is used to set the output
impedance of the high current drivers. Selection of R_OIC
resistance value enables the user to adjust high current
H1/H2 driver operation for a specific CCD product.
Rise and Fall times can be adjusted via the R_OIC
resistance setting. This is accomplished by selecting an
ROIC resistance value from 40kΩ to 120kΩ. Actual
rise/fall timing will be the product of driver loading and
interconnect parasitics.
High current driver characteristics, which are normally
affected by temperature and process variations, are kept
to a minimum by the ISL55112 OIC feature.
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FN6649.0
September 23, 2009