ISL6566A Datasheet, PDF (17/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal

ISL6566A
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6566A will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see Electrical Specifications).
5. The VID code must not be 111111 or 111110 in VRM10
mode or 11111 in AMD Hammer or VRM9 modes. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either
of these codes and will execute soft-start upon receiving
any other code. These codes can be used to enable or
disable the controller but it is not recommended. After
receiving one of these codes, the controller executes a
2-cycle delay before changing the overvoltage trip level to
the shut-down level and disabling PWM. Overvoltage
shutdown cannot be reset using one of these codes.
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles
between enabling the chip and the start of the ramp, the
output voltage progresses at a fixed rate of 12.5mV per each
16 PHASE clock cycles.
Thus, the soft-start period (not including the 16 PHASE clock
cycle delay) up to a given voltage, V_DAC, can be
approximated by the following equation
T_SS
=
V_{-----D----A----C-----}⋅_---1_----2_---8_---0_--
f_S
(EQ. 13)
where V_DAC is the DAC-set VID voltage, and f_S is the
switching frequency.
The ISL6566A also has the ability to start up into a pre-
charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
ENLL (5V/DIV)
T1 T2
T3
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6566A-
BASED MULTI-PHASE CONVERTER
IREF
ISUM
ICOMP
R_OCSET
- ^VOCSET ₊
OCSET
+
ISEN
-
-
V_DROOP
+
100uA
+
OC
VDIFF
+1V
-
VID + 150mV
V_OVP
VSEN
+
x1
-
RGND
SOFT-START, FAULT
AND CONTROL LOGIC
-
OV
+
-
UV
+
PGOOD
0.82 x DAC _{ISL6566A INTERNAL CIRCUITRY}
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
17
FN9200.2
July 27, 2005