ISL6566A Datasheet, PDF (16/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal

ISL6566A
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
C _{B O O T _CAP}
≥
----------^Q-----^G----^A----^T---^E-----------
∆ V_{B O O T _CAP}
(EQ. 12)
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_---
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ∆V_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆V_{BOOT_CAP} (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6566A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, EN_PH3, VCC, PVCC and the VID pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state. This forces the drivers to short gate-
to-source of the upper and lower MOSFET’s to assure the
MOSFETs remain off. The following input conditions must be
met before the ISL6566 is released from this shutdown
mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6566A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6566A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
ISL6566A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
POR
CIRCUIT
PVCC1
+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
ENLL
1.40kΩ
0.66V
SOFT-START
+
AND
-
FAULT LOGIC
EN_PH3
1.22V
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
2. The voltage on ENLL must be above 0.66V. The ENLL
input allows for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6566A in shutdown until the
voltage at ENLL rises above 0.66V. The enable
comparator has 60mV of hysteresis to prevent bounce.
3. The voltage on the EN_PH3 pin must be above 1.22V.
The EN_PH3 input allows for power sequencing between
the controller and the external driver.
4. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
16
FN9200.2
July 27, 2005