ISL6446IAZ-TK Datasheet, PDF (17/19 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
Figure 27 shows an asymptotic plot of the DC/DC converter’s gain vs
frequency. The actual Modulator Gain has a high gain peak
dependent on the quality factor (Q) of the output filter, which is not
shown. Using the previously mentioned guidelines should yield a
compensation gain similar to the curve plotted. The open loop error
amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the log-log
graph of Figure 27 by adding the modulator gain, G_MOD (in dB), to
the feedback compensation gain, G_FB (in dB). This is equivalent to
multiplying the modulator transfer function and the compensation
transfer function and then plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
V_IN
ISL6446
UGATE
PHASE
LGATE
PGND
Q1
L_OUT
V_OUT
C_IN
Q2
C_OUT
RETURN
FIGURE 28. PRINTED CIRCUIT BOARD POWER AND GROUND
PLANES OR ISLANDS
20
log
⎛
⎝
RR-----21--_⎠⎞
0
LOG
20log ^d----^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
G_FB
G_CL
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 27. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of the
switching frequency, F_SW.
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another can
generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
Figure 28 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of ground or power plane
in a printed circuit board. The components shown in Figure 28
should be located as close together as possible. Please note that
the capacitors C_IN and C_OUT each represent numerous physical
capacitors. Locate the ISL6446 within 1 inch of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6446 must be sized to handle up to 2A
peak current.
C_VCC
PGND
R_RT C_SS
VCC
BOOT
C_{BOOT CIN}
ISL6446
SS ^PHASE
RT
VIN
+V_IN
SGND PGND
C_VIN
SGND
+V_IN
Q1 _LOUT
V_OUT
Q2 ^COUT
PGND
FIGURE 29. PRINTED CIRCUIT BOARD POWER AND GROUND
PLANES OR ISLANDS
Figure 29 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction for
the circuits shown. Locate the RT resistor as close as possible to
the RT pin and the SGND pin. Provide local decoupling between
VCC and GND pins.
For each switcher, minimize any leakage current paths on the
SS/EN pin and locate the capacitor, C_SS close to the SS/EN pin
because the internal current source is only 30µA. All of the
compensation network components for each switcher should be
located near the associated COMP and FB pins. Locate the
capacitor, C_BOOT as close as practical to the BOOT and PHASE
pins (but keep the noisy PHASE plane away from the IC (except
for the PHASE pin connection).
The OCSET circuits (see Figure 4 on page 5) should have a
separate trace from the upper FET to the OCSET R and C; that will
more accurately sense the VIN at the FET than just tying them to
the VIN plane. The OCSET R and C should be placed near the IC
pins.
17
FN7944.1
October 15, 2013