ISL6446IAZ-TK Datasheet, PDF (13/19 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
Output Regulation
Figure 23 shows the generic feedback resistor circuit for any of
the two PWM V_OUT’s; the V_OUT is divided down to equal the
reference. All three use a 0.6V internal reference (check the
“Electrical Specifications” Table on page 6 for the exact reference
value at 24V). The R_UP is connected to the V_OUT; the R_LOW to
GND; the common point goes to the FB pin.
V_OUT
R_UP
FB
COMP
EA
R_LOW
0.6V
FIGURE 23. OUTPUT REGULATION
V_OUT must be greater than 0.6V and 2 resistors are needed, and
their accuracy directly affect the regulator tolerance.
FB
=
V_OUT
⋅
----------^R----^L----^O----^W-------------
R_UP + R_LOW
(EQ. 5)
Use Equation 6 to choose the resistor values. R_UP is part of the
compensation network for the switchers, and should be selected
to be compatible; 1kΩ to 5kΩ is a good starting value. Find FB
from the “Electrical Specifications” Table on page 7 (for the right
condition), plug in the desired value for V_OUT, and solve for R_LOW.
R_LOW
=
---^F----^B------^â‹---^R----^U-----^P----
V_OUT – FB
(EQ. 6)
The maximum duty cycle of the ISL6446 approaches 100% at
low frequency, but falls off at higher frequency; see the
“Electrical Specifications” Table on page 7. In addition, there is a
minimum UGATE pulse width, in order to properly sense
overcurrent. The two switchers are 180° out of phase.
Linear Regulator
The linear regulator controller is a trans-conductance amplifier
with a nominal gain of 2A/V. The N-Channel MOSFET output
buffer can sink a minimum of 50mA.
The reference voltage is 0.6V. With 0V differential at its input, the
controller sinks 21mA of current. For better load regulation, it is
recommended that the resistor from the LDO input to the base of
the PNP (or gate of the PFET) is set so that the sink current at G4
pin is within 9mA to 31mA over the entire load and temperature
range.
An external PNP transistor or P-Channel MOSFET pass device can
be used. The dominant pole for the loop can be placed at the
base of the PNP (or gate of the PFET), as a capacitor from
emitter-to-base (source to gate of a PFET). Better load transient
response is achieved however, if the dominant pole is placed at
the output with a capacitor to ground at the output of the
regulator.
60
50
40
30
20
10
0
0.59
0.6
0.61 0.62
0.63 0.64
FEEDBACK VOLTAGE (V)
0.65
FIGURE 24. LINEAR CONTROLLER GAIN
Protection Mechanisms
OCP - (Function independent for both PWM). The overcurrent
function protects the PWM Converter from a shorted output by
using the upper MOSFET’s ON-resistance, r_DS(ON) to monitor the
current. This method enhances the converter’s efficiency and
reduces cost by eliminating a current sensing resistor. The
overcurrent function latches off the outputs to provide fault
protection. A resistor connected to the drain of the upper MOSFET
and OCSET pin programs the overcurrent trip level. The PHASE
node voltage will be compared against the voltage on the OCSET
pin, while the upper MOSFET is on. A current (typically 110µA) is
pulled from the OCSET pin to establish the OCSET voltage. If
PHASE is lower than OCSET while the upper MOSFET is on then an
overcurrent condition is detected for that clock cycle. The upper
gate pulse is immediately terminated, and a counter is
incremented. If an overcurrent condition is detected for 32
consecutive clock cycles, the ISL6446 output is latched off with
gate drivers three-stated. The switcher will restart when the SS/EN
pin is externally driven below 1V, or if power is recycled to the chip.
During soft-start, both pulse termination current limiting and the
32-cycle counter are enabled.
UVP - (Function independent for both PWM). If the voltage on the
FB pin falls to 82% (typical) of the reference voltage for 8
consecutive PWM cycles, then the circuit enters into soft-start
hiccup mode. During hiccup, the external capacitor on the SS/EN
pin is discharged, then released and a soft-start cycle is initiated.
The UVP comparator is separate from the one sensing for PGOOD,
which should have already detected a problem, before the UVP
trips.
OVP - (Function independent for both PWM). OVP function is
enabled after the soft start has finished. If voltage on the FB pin
rises to 116% (typical) of the reference voltage, the lower gate
driver is turned on continuously. If the overvoltage condition
continues for 32 consecutive PWM cycles, then that output is
latched off with the gate drivers three-stated. The capacitor on the
SS/EN pin will not be discharged. The switcher will restart when
the SS/EN pin is externally driven below 1V, or if power is recycled
to the chip. The OVP comparator is separate from the one sensing
for PGOOD, which should have already detected a problem,
before the OVP trips.
13
FN7944.1
October 15, 2013