ISL6446IAZ-TK Datasheet, PDF (11/19 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
Typical Performance Curves
Oscilloscope plots are taken using the ISL6446EVAL1Z evaluation board, V_IN = 12V, V_OUT1 = 5V, V_OUT2 = 3.3V, f_s = 300kHz, unless
otherwise noted. (Continued)
V_IN = 12V
V_OUT1 = 5V
I_OUT = S/C
EN/SSx
I_L
V_IN = 12V
V_OUT1 = 5V
I_OUT = 10, FB = 1V
EN/SSx
V_OUT
I_L
V_OUT
PHASE
PHASE
FIGURE 16. START-UP WITH OC
FIGURE 17. OVERVOLTAGE PROTECTION
Functional Description
Soft-Start and Voltage Tracking
After the VCC pin exceeds its rising POR trip point (nominal 4.4V),
the chip operation begins. Both 30µA current sources will start
charging up the soft-starting capacitors respectively. The charging
continues until the voltage across the soft-start capacitor reaches
about 3.2V. From 1.0V to 1.6V, the outputs will ramp individually
from zero to full-scale. Now, if V = 0.6V, C = 0.1µF, and I = 30µA,
then t = 2ms. Figure 18 shows the typical waveforms for SS2/EN2
and V_OUT2; SS1/EN1 and V_OUT1 are similar.
SS2/EN2 (0.5V/DIV)
1.6V
1.0V
V_OUT2 (2V/DIV)
GND>
FIGURE 18. SOFT-START
The soft-start ramps for each output can be selected
independently. The basic timing is shown in Equation 2:
t
=
C
•
d_----V_---
I
where:
t is the charge time
C is the external capacitance
dV is the voltage charged
I is the charging current (nominal 30µA)
11
(EQ. 2)
Finally, there is a delay after 1.6V, until the ramp gets to ~3.2V,
which signals that the ramp is done; when both ramps are done,
the PGOOD delay begins. To guarantee the soft-start is
completed, please make sure the EN/SSx pin voltage is able to
reach above 3.2V at normal operation.
V_OUT2 (1V/DIV)
GND>
1.6V
1.0V
SS1/EN1 (0.5V/DIV)
V_OUT (1V/DIV)
SS2/EN2 (0.5V/DIV)
GND>
FIGURE 19. VOLTAGE TRACKING
Figure 20 shows pre-biased outputs before soft-start. The solid
blue curve shows no pre-bias; the output starts ramping from
GND. The magenta dotted line shows the output pre-biased to a
voltage less than the final output. The FETs don’t turn on until the
soft-start ramp voltage exceeds the output voltage; then the
output starts ramping seamlessly from there. The cyan dotted
line shows the output pre-biased above the final output (but
below the OVP (Overvoltage Protection)). The FETs will not turn on
until the end of the soft-start ramp; then the output will be
quickly pulled down to the final value.
If the output is pre-biased above the OVP level, the ISL6446 will go
into OVP at the end of soft-start, which will keep the FETs off. See
“Protection Mechanisms” on page 13 for more details.
FN7944.1
October 15, 2013