ISL6446IAZ-TK Datasheet, PDF (12/19 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
VOUT1 has the same functionality as previously described for
VOUT2. Each output should react independently of the other,
unless they are related by the circuit configuration.
.
GND>
PGOOD (5V/DIV)
SS2/EN2 (0.5V/DIV)
V_OUT2 OVER-CHARGED
V_OUT2 PRE-BIASED
V_OUT2 (2V/DIV)
GND>
GND>
GND>
V_OUT3 (2V/DIV)
V_OUT2 (2V/DIV)
V_OUT1 (2V/DIV)
GND>
FIGURE 20. SOFT-START WITH PRE-BIAS
The linear output does not have a soft-start ramp; however, it
may follow the ramp of its input supply, if timed to coincide with
its rise, after the VCC rising POR trip. If the input to the linear is
from one of the two switcher outputs, then it will share the same
ramp rate as the switcher.
PGOOD
A group of comparators (separate from the protection
comparators) monitor the output voltages (via the FB pins) for
PGOOD. Each switcher has a lower and upper boundary
(nominally around 90% and 110% of the target value) and the
linear has a lower boundary (around 75% of the target). Once
both switcher output ramps are done, and all 3 outputs are
within their expected ranges, the PGOOD will start an internal
timer, with Equation 3:
t_PGOOD
=
0_----._-0_----6_---5_--
F_SW
(EQ. 3)
where:
t_PGOOD is the delay time (in sec)
F_SW is the switching frequency (in MHz)
Once the time-out is complete, the internal pull-down device will
shut off, allowing the open-drain PGOOD output to rise through an
external pull-up resistor, to a 5V (or lower) supply, which signals
that the “Power is GOOD”. Figure 21 shows the three outputs
turning on, and the delay for PGOOD. If any of the conditions is
subsequently violated, then PGOOD goes low. Once the voltage
returns to the normal region, a new delay will start, after which the
PGOOD will go high again.
The PGOOD delay is inversely proportional to the clock frequency.
If the clock is running as slow as 524kHz, the delay will be
125ms long. There is no way to adjust the PGOOD delay
independently of the clocK.
FIGURE 21. PGOOD DELAY
Switching Frequency
The switching frequency of the ISL6446 is determined by the
external resistor placed from the RT pin to SGND. See Figure 22
for a graph of Frequency vs RT Resistance. Use Equation 4 to
calculate the approximate RT resistor value for the desired
switching frequency. The typical resistance for 100kHz operation
is 163kΩ. Running at both high frequency and high V_IN voltages
is not recommended, due to the increased power dissipation
on-chip (mostly from the internal VCC regulator, which supplies
gate drivers). The user should check the maximum acceptable IC
temperature, based on their particular conditions.
R_T
=
⎛
⎝
1^--F--1^--S-2^---W-9^---0^{--⎠⎞}
–1.093
(EQ. 4)
300k
100k
50k
30k
10k
3k
100k
200k
500k
1M
2M
SWITCHING FREQUENCY (Hz)
FIGURE 22. FREQUENCY vs R_T RESISTOR
12
FN7944.1
October 15, 2013