HC55171_03 Datasheet, PDF (16/20 Pages) Intersil Corporation – 5 REN Ringing SLIC for ISDN Modem/TA and WLL

HC55171
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LOOP IMPEDANCE
FIGURE 15. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 5
Low Level Ringing Interface
The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.
Loop Detector Interface
The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and
setting F0 low for the entire duration of the ringing period.
The modifications to the application circuit for the single
detector interface are shown in Figure 16.
HC55171
ADDITIONAL PULL UP RESISTOR
NU 23
RDI 20
RDO 21
V_RING 24
V_CC
D_TRAP
R_TRAP
C_TRAP
V_RING
Additional Application Information
(DUAL DETECTOR INTERFACE)
MODE ACTIVE
(LOGIC HI)
F1 _{(LOGIC HI)}
F0
RINGING
V_RING
VALID DET
SHD
RTD
ACTIVE
SHD
MODE
(SINGLE DETECTOR INTERFACE)
ACTIVE
RINGING
(LOGIC HI)
F1 _{(LOGIC HI)}
F0
V_RING
VALID DET
SHD
SHD
ACTIVE
SHD
FIGURE 17. DETECTOR LOGIC INTERFACES
Tip-to-Ring Open Circuit Voltage
The tip-to-ring open-circuit voltage, V_OC, of the HC55171
may be programmed to meet a variety of applications. The
design of the HC5517 defaults the value of V_OC to:
V_OC ≅ V_BAT – 8
Using a zener diode clamping circuit, the default open circuit
voltage of the SLIC may be defeated. Some applications that
have to meet Maintenance Termination Unit (MTU)
compliance have a few options with the HC55171. One
option is to reduce the ringing battery voltage until MTU
compliance is achieved. Another option is to use a zener
clamping circuit on V_REF to over ride the default open circuit
voltage when operating from a high battery.
If a clamping network is used it is important that it is disabled
during ringing. The clamping network must be disabled to
allow the SLIC to achieve its full ringing capability. A zener
clamping circuit is provided in Figure 18.
FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE
LOOP DETECTOR INTERFACE
SLIC Operating State During Ringing
The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector
interface). Figure 17 shows the control interface for the dual
detector interface and the single detector interface.
HC55171
C_IL
V_REF 3
+5V
47kΩ
2N2907
EN
FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE
16