HC55171_03 Datasheet, PDF (15/20 Pages) Intersil Corporation – 5 REN Ringing SLIC for ISDN Modem/TA and WLL

HC55171
by the addition of protection resistors in series with the Tip
and Ring outputs. The amount of protection resistance that
is added will subtract directly from the loop length. For
example if 30Ω protection resistors is used in each of the Tip
and Ring leads, the ringing loop length will decrease by a
total of 60Ω. Therefore, subtracting 60Ω from the graphs will
provide the reduced loop length data.
Lab Measurements
The lab measurements of the trapezoidal ringing circuit were
made with the crest factor programming resistor set to 0Ω
and the battery voltage set to -80V. The Bellcore suggested
REN model was used to simulate the various ringing loads.
A resistor in series with the Tip terminal was used to emulate
loop length.
A logic gate is used to drive the RC shaping network. When
the crest factor programming resistor is set to 0Ω, the output
impedance of the logic gate results in a 0.8V/ms slewing
voltage on C_TRAP .
Each graph shows the RMS ringing voltage into a fixed REN
load versus loop length. The ringing voltage was measured
across the test load. Each test also verified proper operation
of the ring trip detector. Proper ring trip detector operation is
defined as a constant logic high while ringing and on hook
and a constant logic low when off hook is detected. The
component values in the application circuit provide a ring trip
response in the 100ms to 150ms range.
60
59
58
56
54
52
50
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 12. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 2
58
55
52
49
46
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 13. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 3
58
55
57
52
56
49
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 11. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 1
46
43
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 14. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 4
15