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HC55171_03 Datasheet, PDF (12/20 Pages) Intersil Corporation – 5 REN Ringing SLIC for ISDN Modem/TA and WLL | |||
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HC55171
IR
=
â----4---(---R-----S----â----I--L----)
R


ï£
R-R----R-Z----0F--
+
V-----R-----X--
R
IR
R
R
VRX
1VP
R
OUT1
+ âIL - + âIL -
RP1
RS1
TIP
A
-
+
-
+ VC
R/20
VRING
R/2
VC
=
â4
RS

âI L ï£ï£¬
R-R----R-Z----0F--
+
VRX
â
+
-
2VDC
IOUT1 =
4RSâIL
2R
RZ0
RRF
VTR RL
âVIN
+
-
-
+RSâIL
-
RZ0
+
âIL
RRF
+
RP1 = RP2 = RS1 = RS2 = RS
+
-
2
VTX
-IN1
-
+
-
âIL
+
90k⦠90kâ¦
+
-
-RSâIL
+
4R-SâIL
-
4RSâIL
+
RZ0
RRF
B
RP2
RING
- âIL +
RS2
- âIL +
-
+
+
- VD
VD
=
4RS

âI L ï£ï£¬
R-R----R-Z----0F--
â VRX
â
-
+
VBAT
2
â GROUNDED FOR AC ANALYSIS
FIGURE 7. AC VOLTAGE GAIN AND IMPEDANCE MATCHING
The net effect cancels out the voltage drop across the feed
resistors. By nullifying the effects of the feed resistors the
feedback circuitry becomes relatively easy to match the
impedance at points âAâ and âBâ.
Impedance Matching Design Equations
âVIN
+
-
RL
LOAD
SLIC
8RSï£ï£¬ï£«R-R----R-Z----0F-- + 4RS
Matching the impedance of the SLIC to the load is
accomplished by writing a loop equation starting at VD and
going around the loop to VC .
The loop equation to match the impedance of any load is as
follows (note: VRX = 0 for this analysis):
â4RS
âIL


ï£
R-R----R-Z---0F--
+
2 RS âIL â âVI N
+
R L âIL
+
2
RS
âIL
â4
RS
âIL


ï£
R-R----R-Z---0F--
(EQ. 20)
âVIN
=
â8
RS
âIL


ï£
R-R----R-Z---0F--
+ 4RSâIL + RLâIL
âVIN
=
âIL
â8
RS


ï£
R-R----R-Z---0F--
+
4RS
+
RL
(EQ. 21)
(EQ. 22)
FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20
The result is shown in Equation 23. Figure 8 is a schematic
representation of Equation 18. To match the impedance of
the SLIC to the impedance of the load, set:
8

R S ï£ï£¬
R-R----R-Z---0F--
+
4RS
=
RL
(EQ. 24)
If RRF is made to equal 8RS then:
RZ0 + 4RS = RL
(EQ. 25)
Therefore to match the HC5517, with RS equal to 50⦠, to a
600⦠load:
RRF = 8RS = 8(50â¦) = 400â¦
(EQ. 26)
Equation 22 can be separated into two terms, the feedback
(-8RS(RZ0/RRF)) and the loop impedance (+4RS+RL).
-â---V----I--N--
âIL
=
â8

R S ï£ï£¬
R-R----R-Z---0F--
+ [4RS + RL]
(EQ. 23)
and
RZ0 = RLâ4RS = 600⦠â 200⦠= 400â¦
(EQ. 27)
To prevent loading of the VTX output, the value of RZ0 and
RRF are typically scaled by a factor of 100:
KRZ0 = 40kâ¦
KRRF = 40kâ¦
(EQ. 28)
12
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