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HC55171_03 Datasheet, PDF (12/20 Pages) Intersil Corporation – 5 REN Ringing SLIC for ISDN Modem/TA and WLL
HC55171
IR
=
–----4---(---R-----S----∆----I--L----)
R



R-R----R-Z----0F--
+
V-----R-----X--
R
IR
R
R
VRX
1VP
R
OUT1
+ ∆IL - + ∆IL -
RP1
RS1
TIP
A
-
+
-
+ VC
R/20
VRING
R/2
VC
=
–4
RS

∆I L 
R-R----R-Z----0F--
+
VRX
†
+
-
2VDC
IOUT1 =
4RS∆IL
2R
RZ0
RRF
VTR RL
∆VIN
+
-
-
+RS∆IL
-
RZ0
+
∆IL
RRF
+
RP1 = RP2 = RS1 = RS2 = RS
+
-
2
VTX
-IN1
-
+
-
∆IL
+
90kΩ 90kΩ
+
-
-RS∆IL
+
4R-S∆IL
-
4RS∆IL
+
RZ0
RRF
B
RP2
RING
- ∆IL +
RS2
- ∆IL +
-
+
+
- VD
VD
=
4RS

∆I L 
R-R----R-Z----0F--
– VRX
†
-
+
VBAT
2
† GROUNDED FOR AC ANALYSIS
FIGURE 7. AC VOLTAGE GAIN AND IMPEDANCE MATCHING
The net effect cancels out the voltage drop across the feed
resistors. By nullifying the effects of the feed resistors the
feedback circuitry becomes relatively easy to match the
impedance at points “A” and “B”.
Impedance Matching Design Equations
∆VIN
+
-
RL
LOAD
SLIC
8RSR-R----R-Z----0F-- + 4RS
Matching the impedance of the SLIC to the load is
accomplished by writing a loop equation starting at VD and
going around the loop to VC .
The loop equation to match the impedance of any load is as
follows (note: VRX = 0 for this analysis):
–4RS
∆IL



R-R----R-Z---0F--
+
2 RS ∆IL – ∆VI N
+
R L ∆IL
+
2
RS
∆IL
–4
RS
∆IL



R-R----R-Z---0F--
(EQ. 20)
∆VIN
=
–8
RS
∆IL



R-R----R-Z---0F--
+ 4RS∆IL + RL∆IL
∆VIN
=
∆IL
–8
RS



R-R----R-Z---0F--
+
4RS
+
RL
(EQ. 21)
(EQ. 22)
FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20
The result is shown in Equation 23. Figure 8 is a schematic
representation of Equation 18. To match the impedance of
the SLIC to the impedance of the load, set:
8

R S 
R-R----R-Z---0F--
+
4RS
=
RL
(EQ. 24)
If RRF is made to equal 8RS then:
RZ0 + 4RS = RL
(EQ. 25)
Therefore to match the HC5517, with RS equal to 50Ω , to a
600Ω load:
RRF = 8RS = 8(50Ω) = 400Ω
(EQ. 26)
Equation 22 can be separated into two terms, the feedback
(-8RS(RZ0/RRF)) and the loop impedance (+4RS+RL).
-∆---V----I--N--
∆IL
=
–8

R S 
R-R----R-Z---0F--
+ [4RS + RL]
(EQ. 23)
and
RZ0 = RL–4RS = 600Ω – 200Ω = 400Ω
(EQ. 27)
To prevent loading of the VTX output, the value of RZ0 and
RRF are typically scaled by a factor of 100:
KRZ0 = 40kΩ
KRRF = 40kΩ
(EQ. 28)
12