D2-24044 Datasheet, PDF (16/20 Pages) Intersil Corporation – Digital Audio Amplifier Power Stage

Channel 1
PWM Input
PWMIN1-HI
PWMIN1-LO
Channel 2
PWM Input
PWMIN2-HI
PWMIN2-LO
Channel 3
PWM Input
PWMIN3-HI
PWMIN3-LO
PWM Inputs From
PWM/System Controller
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM1-8
Input Pins
D2-24044
PWM Input Mapping To Output Stages
Configuration “10”
2 x Half-Bridge Outputs + 1 x Full Bridge Output
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTA
Channel 1
Output
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTB
Channel 2
Output
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTC
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTD
Channel 2
Output
FIGURE 13. CONFIGURATION “10” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
Channel 1
PWM Input
PWMIN1-HI
PWMIN1-LO
Channel 2
PWM Input
PWMIN2-HI
PWMIN2-LO
Channel 3
PWM Input
PWMIN3-HI
PWMIN3-LO
Channel 3
PWM Input
PWMIN4-HI
PWMIN4-LO
PWM Inputs From
PWM/System Controller
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM1-8
Input Pins
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTA
Channel 1
Output
PWM Input Mapping To Output Stages
Configuration “11”
4x Half-Bridge Outputs
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTB
Channel 2
Output
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTC
Channel 3
Output
(HVDD)
High
Side
FET
Low
Side
FET
(HGND)
OUTD
Channel 4
Output
FIGURE 14. CONFIGURATION “11” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
16
FN7678.0
September 3, 2010