D2-24044 Datasheet, PDF (14/20 Pages) Intersil Corporation – Digital Audio Amplifier Power Stage

D2-24044
Output Mode Configurations
The D2-24044 device supports four amplifier output
configuration modes, utilizing the device’s 4 power stage
outputs.
Configuration selection is controlled by the OCFG0 and
OCFG1 pins, by connecting them to either a high
(+3.3V, PWMVDD = 1) or low (ground = 0) level.
Settings are chosen based on the output configuration
and topology of the design. Their connection is to be
hard-connected on the design, and they are not
intended to be dynamic or subject to change during
system operation.
For each of the four configurations, the PWM input pin
signals route to the individual FETs of each of the power
stages to implement the channel drive and topology
needed for those configurations. Figures 11, 12, 13, and
14 show this routing of the PWM inputs to each of the
power stages, and how the particular topology is
implemented for that configuration. Table 1 shows the
configuration functions that are defined with the
combinations of the OCFG pins, and these diagrams
show the implementation that is listed in this table.
TABLE 1. D2-24044 CONFIGURATION PWM AND OUTPUT CHANNEL ASSIGNMENTS
CONFIG PINS
CONFIGURATION
OCFG1 OCFG0 CONFIG DESCRIPTION
POWER STAGE OUTPUT
nERROR CHANNEL USE
OUTA OUTB OUTC OUTD nERRORA nERRORB nERRORC nERRORD
0
0
“00”
2-Channel
Full Bridge
3-Level
PWM Drive
Output
Channel 1
Output
Channel 2
High-Side FET PWM Input Assignments
PWM1 PWM3 PWM5 PWM7
Connect (wire-or)
Connect (wire-or)
nERRORA & nERRORB nERRORC & nERRORD
together.
together.
Use for Output
Use for Output
Channel 1 Protect
Channel 2 Protect
(Ref. Figure 11)
Low-Side FET PWM Input Assignments
PWM2 PWM4 PWM6 PWM8
Output
Output
Connect (wire-or)
Connect (wire-or)
Channel 1
Channel 2
nERRORA & nERRORB nERRORC & nERRORD
2-Channel
Full Bridge,
High-Side FET PWM Input Assignments
together.
Use for Output
together.
Use for Output
0
1
“01” 2-Quadrant PWM Drive _{PWM1 PWM2 PWM3 PWM4}
Channel 1 Protect
Channel 2 Protect
(Ref. Figure 12)
Low-Side FET PWM Input Assignments
PWM2 PWM1 PWM4 PWM3
Output Output
Output
2-Channel
Ch. 1
Ch 2
Channel 3
1
0
“10”
Half-Bridge
plus
1-Channel
Full Bridge
High-Side FET PWM Input Assignments
PWM1 PWM3 PWM5 PWM6
Low-Side FET PWM Input Assignments
nERRORA
Use for
Channel 1
Protect
nERRORB
Use for
Channel 2
Protect
Connect (wire-or)
nERRORC & nERRORD
together.
Use for Output
Channel 3 Protect
(Ref. Figure 13)
PWM2 PWM4 PWM6 PWM5
Output Output Output Output
Ch. 1
Ch 2
Ch. 3
Ch 4
1
1
“11”
4-Channel
Half-Bridge
High-Side FET PWM Input Assignments ^{nERRORA nERRORB nERRORC nERRORD}
Use for Use for Use for Use for
PWM1 PWM3 PWM5 PWM7 Channel 1 Channel 2 Channel 3 Channel 4
(Ref. Figure 14)
Low-Side FET PWM Input Assignments
Protect
Protect
Protect
Protect
PWM2 PWM4 PWM6 PWM8
14
FN7678.0
September 3, 2010