HC5513_03 Datasheet, PDF (15/20 Pages) Intersil Corporation – TR909 DLC/FLC SLIC with Low Power Standby

HC5513
TABLE 1. LOGIC TRUTH TABLE
E0
E1
C1
C2
SLIC OPERATING STATE
ACTIVE DETECTOR
1
0
0
0
Open Circuit
No Active Detector
1
0
0
1
Active
Ground Key Detector
1
0
1
0
Ringing
No Active Detector
1
0
1
1
Standby
Ground Key Detector
1
1
0
0
Open Circuit
1
1
0
1
Active
1
1
1
0
Ringing
1
1
1
1
Standby
No Active Detector
Loop Current Detector
Ring Trip Detector
Loop Current Detector
DET OUTPUT
Logic Level High
Notes
2. Overload Level (Two-Wire port) - The overload level is speci-
fied at the 2-wire port (V_TR0) with the signal source at the 4-wire
receive port (E_RX). I_DCMET = 30µA, increase the amplitude of
E_RX until 1% THD is measured at V_TRO. Reference Figure 1.
3. Longitudinal Impedance - The longitudinal impedance is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L_ZT, L_ZR, V_T, V_R, A_R and
A_T are defined in Figure 2.
(TIP) L_ZT = V_T/A_T
(RING) L_ZR = V_R/A_R
Where: E_L = 1V_RMS (0Hz to 100Hz).
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
(Active, C₁ = 1, C₂ = 0) longitudinal current limit is determined
by increasing the amplitude of E_L (Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
5. Longitudinal Current Limit (On-Hook Standby) - On-Hook
(Active, C₁ = 1, C₂ = 1) longitudinal current limit is determined by
increasing the amplitude of E_L (Figure 3B) until the 2-wire longitu-
dinal balance drops below 45dB. DET pin remains high (no false
detection).
6. Longitudinal to Metallic Balance - The longitudinal to metal-
lic balance is computed using the following equation:
BLME = 20 • log (E_L/V_TR), where: E_L and V_TR are defined in
Figure 4.
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
metallic to longitudinal balance is defined in this spec.
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
balance is computed using the following equation:
BLFE = 20 • log (E_L/V_TX),: E_L and V_TX are defined in Figure 4.
9. Metallic to Longitudinal Balance - The metallic to longitudinal
balance is computed using the following equation:
BMLE = 20 • log (E_TR/V_L), E_RX = 0
Where: E_TR, V_L and E_RX are defined in Figure 5.
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
balance is computed using the following equation:
BFLE = 20 • log (E_RX/V_L), E_TR = source is removed.
Where: E_RX, V_L and E_TR are defined in Figure 5.
11. Two-Wire Return Loss - The 2-wire return loss is computed
using the following equation:
r = -20 • log (2V_M/V_S)
Where: Z_D = The desired impedance; e.g., the characteristic
impedance of the line, nominally 600Ω. (Reference Figure 6).
12. Overload Level (4-Wire port) - The overload level is specified
at the 4-wire transmit port (V_TXO) with the signal source (E_G) at
the 2-wire port, I_DCMET = 23mA, Z_L = 20kΩ (Reference Figure
7). Increase the amplitude of E_G until 1% THD is measured at
V_TXO. Note that the gain from the 2-wire port to the 4-wire port
is equal to 1.
13. Output Offset Voltage - The output offset voltage is specified
with the following conditions: E_G = 0, I_DCMET = 23mA, Z_L = ∞
and is measured at V_TX. E_G, I_DCMET, V_TX and Z_L are defined
in Figure 7. Note: I_DCMET is established with a series 600Ω
resistor between tip and ring.
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