HC5513_03 Datasheet, PDF (13/20 Pages) Intersil Corporation – TR909 DLC/FLC SLIC with Low Power Standby

HC5513
The function of this circuit is to maintain the tip and ring
voltages symmetrically around V_BAT/2, in the presence of
longitudinal currents. The differential transconductance
amplifiers G_T and G_R accomplish this by sourcing or sinking
the required current to maintain V_C at V_BAT/2.
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at V_C moves from it’s equilibrium value
V_BAT/2. When V_C changes by the amount ∆V_C, this change
appears between the input terminals of the differential
transconductance amplifiers G_T and G_R. The output of G_T
and G_R are the differential currents ∆I₁ and ∆I₂, which in
turn feed the differential inputs of current sources I_T and I_R
respectively. I_T and I_R have current gains of 250 single
ended and 500 differentially, thus leading to a change in I_T
and I_R that is equal to 500(∆_I) and 500(∆I₂).
The circuit shown in Figure 20(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
to current source 2I_O is now correlated, power savings due
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5513 has two enable inputs pins (E0, E1)
and two control inputs pins (C1, C2).
The enable pin E0 is used to enable or disable the DET
output pin. The DET pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
The enable pin E1 gates the ground key detector to the DET
output with a logic level 0, and gates the loop or ring trip
detector to the DET output with a logic level 1.
I_{LONG ILONG}
TIP
+
∆V_T-
R_LARGE
I_T
∆I₁
∆I₁
G_T
I_LONG
V_C ⁺
-
V_BAT/2
R_LARGE
I_LONG
∆I₂
G_R
∆I₂
+ ^RING
∆V_R
I_R
- _HC5513
A combination of the control pins C1 and C2 is used to select
1 of the 4 possible operating states. A description of each
operating state and the control logic follow:
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and both
the tip and ring line drive amplifiers are powered down,
presenting a high impedance to the line. Power dissipation is
at a minimum.
Active State (C1 = 0, C2 = 1)
The tip output is capable of sourcing loop current and for open
circuit conditions is about -4V from ground. The ring output is
capable of sinking loop current and for open circuit conditions is
about V_BAT + 4V. VF signal transmission is normal. The loop
current and ground key detectors are both active, E0 and E1
determine which detector is gated to the DET output.
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and ring
to V_BAT to allow loop current detect in an off-hook condition.
The loop current and ground key detectors are both active, E0
and E1 determine which detector is gated to the DET output.
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
compensation capacitors C_TC and C_RC are required.
Figure 21 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
TIP
R_LARGE
V_C
R_LARGE
RING
TIP CURRENT SOURCE
WITH DIFFERENTIAL INPUTS
20Ω
5kΩ ^5kΩ
-
+
∆I₁
∆I₁
V_BAT/2
2I₀
G_T
TIP DIFFERENTIAL
TRANSCONDUCTANCE
AMPLIFIER
FIGURE 20A.
FIGURE 20. LONGITUDINAL IMPEDANCE NETWORK
FIGURE 20B.
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