X40010 Datasheet, PDF (13/24 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor

X40010, X40011, X40014, X40015
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Figure 14. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
A
C
K
1
A
C
K
Data
(1)
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
S
t
o
A
A
p
C
C
K
K
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
13
FN8111.0
March 28, 2005