ISL62882 Datasheet, PDF (12/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62882, ISL62882B
Theory of Operation
Multiphase R^3™ Modulator
VW
Master Clock Circuit
Master
Master ^COMP
Clock _Phase
Clock _Vcrm
Sequencer
gmVo
Crm
Clock1
Clock2
VW
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
Slave Circuit 1
Clock1 S PWM1 ^{Phase1 L1}
RQ
IL1
gm
Slave Circuit 2
Clock2 S PWM2Phase2 ^L2
Q
R
I_L2
gm
Vo
Co
FIGURE 5. R³â„¢ MODULATOR CIRCUIT
VW
Vcrm
COMP
Master
Clock
Clock1
PWM1
Clock2
PWM2
VW
Hysteretic
Window
Vcrs2 Vcrs1
FIGURE 6. R^3™ MODULATOR OPERATION
PRINCIPLES IN STEADY STATE
Vcrm
Master
Clock
Clock1
PWM1
Clock2
PWM2
VW
COMP
VW
Vcrs1
Vcrs2
FIGURE 7. R³â„¢ MODULATOR OPERATION
PRINCIPLES IN LOAD INSERTION
RESPONSE
The ISL62882 is a multiphase regulator implementing
Intel^® IMVP-6.5^™ protocol. It can be programmed for
1- or 2-phase operation for microprocessor core
applications. It uses Intersil patented R^3™ (Robust
Ripple Regulator^™) modulator. The R^3™ modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. Figure 5 conceptually shows the
ISL62882 multiphase R^3™ modulator circuit, and Figure
6 shows the operation principles.
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
the two pins. This voltage window is called VW window in
the following discussion.
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor C_rm with a
current source equal to g_mV_o, where g_m is a gain factor.
C_rm voltage V_crm is a sawtooth waveform traversing
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot master
clock signal. A phase sequencer distributes the master
clock signal to the slave circuits. If the ISL62882 is in 2-
phase mode, the master clock signal will be distributed to
Phases 1 and 2, and the Clock1 and Clock2 signals will be
180° out-of-phase. If the ISL62882 is in 1-phase mode,
the master clock signal will be distributed to Phases 1
only and be the Clock1 signal.
Each slave circuit has its own ripple capacitor C_rs, whose
voltage mimics the inductor ripple current. A g_m
amplifier converts the inductor voltage into a current
source to charge and discharge C_rs. The slave circuit
turns on its PWM pulse upon receiving the clock signal,
and the current source charges C_rs. When C_rs voltage
12
FN6890.2
April 29, 2010