ISL62881C_14 Datasheet, PDF (12/37 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62881C, ISL62881D
Theory of Operation
Multiphase R^3™ Modulator
VW
MASTER CLOCK CIRCUIT
MASTER ^COMP
CLOCK _VCRM
CLOCK
GMVO
CRM
SLAVE CIRCUIT
VW
CLOCK SQ PWM
L
R
PHASE
IL
VCRS
GM
CRS
VO
CO
FIGURE 5. R^3™ MODULATOR CIRCUIT
VW
VCRM
COMP
CLOCK
PWM
VCRS
VW
HYSTERETIC
W IND O W
FIGURE 6. R^3™ MODULATOR OPERATION PRINCIPLES
IN STEADY STATE
VW
VCRM
COMP
CLOCK
PWM
VW
The ISL62881C is a single-phase regulator implementing
Intel^® IMVP-6.5^™ protocol. It uses Intersil patented
R^3™(Robust Ripple Regulator^™) modulator. The R^3™
modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 5 conceptually shows the
ISL62881C R^3™ modulator circuit, and Figure 6 shows
the operation principles.
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
between the two pins. This voltage window is called VW
window in the following discussion.
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuit. The
modulator discharges the ripple capacitor C_rm with a
current source equal to g_mV_o, where g_m is a gain factor.
C_rm voltage V_crm is a sawtooth waveform traversing
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot clock
signal.
The slave circuit has its own ripple capacitor C_rs, whose
voltage mimics the inductor ripple current. A g_m
amplifier converts the inductor voltage into a current
source to charge and discharge C_rs. The slave circuit
turns on its PWM pulse upon receiving the clock signal,
and the current source charges C_rs. When C_rs voltage
V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
Since the ISL62881C works with V_crs, which is large-
amplitude and noise-free synthesized signal, the
ISL62881C achieves lower phase jitter than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL62881C
has an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
Figure 7 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the clock signal more quickly, so the
PWM pulse turns on earlier, increasing the effective
switching frequency, which allows for higher control loop
bandwidth than conventional fixed frequency PWM
controllers. The VW voltage rises as the COMP voltage
rises, making the PWM pulse wider. During load release
response, the COMP voltage falls. It takes the master
clock circuit longer to generate the next clock signal so
the PWM pulse is held off until needed. The VW voltage
falls as the VW voltage falls, reducing the current PWM
pulse width. This kind of behavior gives the ISL62881C
excellent response speed.
VCRS
FIGURE 7. R^3™ MODULATOR OPERATION PRINCIPLES
IN LOAD INSERTION RESPONSE
12
FN7596.0
March 8, 2010