ISL29125_14 Datasheet, PDF (12/17 Pages) Intersil Corporation – Digital Red, Green and Blue Color Light Sensor with IR Blocking Filter

ISL29125
Lower Interrupt Register (Address: 0x04 and 0x05) and Higher Interrupt Register (Address:
0x06 and 0x07)
NAME
Low Threshold-Low byte
Low Threshold- High byte
High Threshold- Low byte
High Threshold-High byte
REGISTER ADDRESS
DEC
HEX
4
0x04
5
0x05
6
0x06
7
0x07
TABLE 14. CONFIGURATION-3
REGISTER BITS
DEFAULT ACCESS
B7
B6
B5
B4
B3
B2
B1
B0
THL[7] THL[6] THL[5] THL[4] THL[3] THL[2] THL[1] THL[0] 0x00
RW
THH[7] THH[6] THH[5] THH[4] THH[3] THH[2] THH[1] THH[0] 0x00
RW
THL[7] THL[6] THL[5] THL[4] THL[3] THL[2] THL[1] THL[0] 0xFF
RW
THH[7] THH[6] THH[5] THH[4] THH[3] THH[2] THH[1] THH[0] 0xFF
RW
Interrupt Threshold (Reg 0x4, Reg0x5, Reg0x6 and Reg0x7)
The interrupt threshold level is a 16-bit number (Low Threshold-1 and Low Threshold-2). The lower interrupt threshold registers are used
to set the lower trigger point for interrupt generation. If the ALS value crosses below or is equal to the lower threshold, an interrupt is
asserted on the interrupt pin (LOW) and the interrupt status bit (HIGH). Registers Low Threshold-1 (0x04 or 0x6) and Low Threshold-2
(0x05 or 0x7) provide the low and high bytes, respectively, of the lower interrupt threshold. The interrupt threshold registers default to
0x00 upon power up. The user can also configure the persistency for the interrupt pin. This reduces the possibility of false triggers, such
as noise or sudden spikes in ambient light conditions or an unexpected camera flash, for example, can be ignored by setting the
persistency to 8 integration cycles.
Status Flag Register (Address: 0x08)
NAME
Status Flag
TABLE 15. STATUS FLAG REGISTER
REGISTER
ADDRESS
REGISTER BITS
DEC HEX
B7
B6
B5
B4
B3
8
0x08 RESERVED RESERVED RGBCF[1] RGBCF[0] RESERVED
B2
BOUTF
B1
CONVENF
DEFAULT ACCESS
B0
RGBTHF 0x04 RO
RGBTHF [B0]
This is the status bit of the interrupt. The bit is set to logic high
when the interrupt thresholds have been triggered (out of
threshold window) and logic low when not yet triggered. Once
activated and the interrupt is triggered, the INT pin goes low and
the interrupt status bit goes high until the status bit is polled
through the I²C read command. Both the INT output and the
interrupt status bit are automatically cleared at the end of the
8-bit (00h) command register transfer
TABLE 16. INTERRUPT FLAG
B0
OPERATION
0
Interrupt is cleared or not triggered yet
1
Interrupt is triggered
CONVENF [B1]
This is the status bit of conversion. The bit is set to logic high
when the conversion have been completed and logic low when
the conversion is not done or not conversion.
TABLE 17. CONVERSION FLAG
B1
OPERATION
0
Still convert or cleared
1
Conversion completed
BOUTF [B2]
Bit2 on register address 0x08 is a status bit for brownout
condition (BOUT). The default value of this bit is HIGH, BOUT = 1,
during the initial power up. This indicates the device may possibly
have gone through a brownout condition. Therefore, the status
bit should be reset to LOW, BOUT = 0, by an I²C write command
during the initial configuration of the device. The default register
value is 0x04 at power-on.
TABLE 18. BROWNOUT FLAG
B2
OPERATION
0
No Brownout
1
Power down or Brownout occurred
RGBCF [B5:B4]
B[5:4] are flag bits to display either Red or Green or Blue is under
conversion process at Table 19.
B5:4
00
01
10
11
TABLE 19. CONVERSION FLAG
RGB UNDER CONVERSION
No Operation
GREEN
RED
BLUE
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FN8424.2
January 24, 2014