ISL29125_14 Datasheet, PDF (11/17 Pages) Intersil Corporation – Digital Red, Green and Blue Color Light Sensor with IR Blocking Filter

.
B7
IR-COM
106
ISL29125
B6
RESERVED
100
90
80
0x80-0xBF-IR
70
60
B[5:0]
IR COMP ADJUST
50
B7 is ‘0’ or ‘1’
IR COMP OFFSET
40
30 0x00-0x3F
20
10
0
0
32
64
96 128 160 192 224 256
COMPENSATION REGISTER (0x02) SET VALUE (DECIMAL)
FIGURE 12. IR COMPENSATION SET
B5
ALSCC[5]
32
B4
ALSCC[4]
16
TABLE 9.
B3
ALSCC[3]
8
B2
ALSCC[2]
4
B1
ALSCC[1]
2
B0
ALSCC[0]
1
LIGHT-WEIGHT
Codes
NOTES:
11. A illuminant is intended to represent typical, domestic, tungsten-filament lighting. Its CCT is about 2856K.
12. D series of illuminants are constructed to represent natural daylight. D65 is used in lab to represent as noon light to test. Its CCT is 6504K.
13. F series of illuminants represent various types of fluorescent lighting. F2 is cool white fluorescent using in lab to test. Its CCT is 4230K.
Configuration-3 Register (Address: 0x03)
TABLE 10. CONFIGURATION-3
NAME
REGISTER ADDRESS
REGISTER BITS
DEFAULT ACCESS
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
CONFIGURATION-3 3
0x03 RESERVED RESERVED RESERVED CONVEN PRST[1] PRST[0] INTSEL[1] INTSEL[0] 0x00 RW
INTERRUPT THRESHOLD ASSIGNMENT [B1:0]
The interrupt status bit (RGBTHF) bit0 at Reg0x08 is a status bit
for light intensity detection. The bit is set to logic HIGH when the
light intensity crosses the interrupt thresholds window (register
address 0x04 - 0x07) and set to logic LOW when its within the
interrupt thresholds window. Once the interrupt is triggered, the
INT pin goes low and the interrupt status bit goes HIGH until the
status bit is polled through the I²C read command. Both the INT
pin and the interrupt status bit are automatically cleared at the
end of the 8-bit Device Register byte (0x08) transfer. Table 11
shows selectable interrupt for the device.
TABLE 11. INTERRUPT STATUS
B1:0
INTERRUPT STATUS
00
No Interrupt
01
GREEN Interrupt
10
RED Interrupt
11
BLUE Interrupt
INTERRUPT PERSIST CONTROL [B3:2]
To minimize interrupt events due to 'transient' conditions, an
interrupt persistency option is available. IN the event of transient
condition an 'X-consecutive' number of interrupt must happen
before the interrupt flag and pint (INT) pin gets driven low. The
interrupt is active-low and remains asserted until the status
register (Addr: 0x08) is read to CLEAR the bit(s).
B3:2
00
01
10
11
TABLE 12. INTERRUPT PERSIST
NUMBER OF INTEGRATION CYCLE
1
2
4
8
RGB CONVERSION DONE TO INT CONTROL [B4]
TABLE 13.
B4
CONVERSION DONE
0
Disable
1
Enable
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FN8424.2
January 24, 2014