X9241A_06 Datasheet, PDF (11/16 Pages) Intersil Corporation – Quad Digital Controlled Potentionmeters (XDCP™)

X9241A
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Capacitance
SYMBOL
PARAMETER
C_I/O (Note 5)
C_IN (Note 5)
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
V_I/O = 0V
V_IN = 0V
TYP
19
12
UNIT
pF
pF
Power-up Timing
SYMBOL
PARAMETER
t_PUR (Note 6)
t_PUW (Note 6)
t_RV_CC
Power-up to initiation of read operation
Power-up to initiation of write operation
V_CC Power up ramp rate
MIN
TYP
MAX
1
5
0.2
50
UNIT
ms
ms
V/ms
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V_CC, then the potentiometer pins. It is suggested that Vcc reach 90% of its
final value before power is applied to the potentiometer pins. The V_CC ramp rate specification should be met, and any glitches or
slope changes in the V_CC line should be held to <100mV if possible. Also, V_CC should not reverse polarity by more than 0.5V.
Notes: (5) This parameter is not 100% tested.
(6) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to
the device.
Equivalent AC Test Circuit
AC Conditions of Test
5V
Input pulse levels
V_CC x 0.1 to V_CC x 0.9
Input rise and fall times
10ns
1533Ω
Input and output timing levels
V_CC x 0.5
SDA Output
Symbol Table
100pF
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
Circuit #3 SPICE Macro Model
Macro Model
R_TOTAL
R_H
R_L
C_H
C_L
15pF
C_W ^15pF
25pF
R_W
11
FN8164.5
December 14, 2006