HCTS164MS_02 Datasheet, PDF (1/8 Pages) Intersil Corporation – Radiation Hardened 8-Bit Serial-In/Parallel-Out Shift Register

TM
HCTS164MS
August 1995
Radiation Hardened
8-Bit Serial-In/Parallel-Out Shift Register
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• Dose Rate Survivability >10¹² RAD (Si)/s (20ns Pulse)
• Dose Rate Upset >10¹⁰ RAD (Si)/s (20ns Pulse)
• Single Event Ray Upset Rate < 2 x 10^-9 Errors/Bit Day
(Typ)
• LET Threshold >100 MEV-cm²/mg
• Latch-Up-Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
-VIL = 0.8 VCC (Max)
-VIH = VCC/2 (Min)
• Input Current Levels Ii ≤5µA at VOL, VOH
Description
The Intersil HCTS164MS is a radiation hardened 8-bit Serial-In/
Parallel-Out Shift Register with asynchronous reset.
The HCTS164MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T14
TOP VIEW
DS1 1
DS2 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
14 VCC
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
8 CP
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835, CDFP3-F14
TOP VIEW
DS1
DS2
Q0
Q1
Q2
Q3
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
Q7
Q6
Q5
Q4
MR
CP
Ordering Information
PART NUMBER
HCTS164DMSR
HCTS164KMSR
HCTS164D/Sample
HCTS164K/Sample
HCTS164HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
Truth Table
OPERATING
MODE
MR
INPUTS
CP
DS1†
DS2†
OUTPUTS
Q0
Q1-Q7
Reset (Clear)
L
X
X
X
L
L-L
Shift
H
L
L
L
q0 -q6
H
L
H
L
q0 - q6
H
H
L
L
q0 - q6
H
H
H
H
q0 - q6
H = High Voltage Level
L = Low Voltage Level
= LOW-to-HIGH clock transition
q = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition
† = DS1 and DS2 inputs must be at state one setup prior to CP (rising edge)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
FN 3386.1
Spec Number 518613