82093AA Datasheet, PDF (8/20 Pages) Intel Corporation – I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

82093AA (IOAPIC)
E
3.0. REGISTER DESCRIPTION
The IOAPIC is addressed with a CS# and the D/I# pin. The PIIX3 decodes the IOAPIC in memory space and
sends a CS# to the IOAPIC device, when it is selected. The D/I# pin selects between the IOREGSEL Register
(D/I#=0) and the IOWIN Register (D/I#=1). Typically, D/I# is connected to SA4 on the ISA bus (i.e., IOREGSEL
Register is at 00h and IOWIN Register is at 10h).
The IOAPIC registers are accessed by an indirect addressing scheme using two registers (IOREGSEL and
IOWIN) that are located in the CPU's memory space (memory address specified by the APICBASE Register
located in the PIIX3). These two registers are re-locateable (via the APICBASE Register) as shown in Table 3.1.
In the IOAPIC only the IOREGSEL and IOWIN Registers are directly accesable in the memory address space.
To reference an IOAPIC register, a byte memory write that the PIIX3 decodes for the IOAPIC loads the
IOREGSEL Register with an 8-bit value that specifies the IOAPIC register (address offset in Table 3.2) to be
accessed. The IOWIN Register is then used to read/write the desired data from/to the IOAPIC register specified
by bits [7:0] of the IOREGSEL Register. The IOWIN Register must be accessed as a Dword quantity.
The IOREGSEL and IOWIN Registers (Table 3.1) can be relocated via the APIC Base Address Relocation
Register in the PIIX3 and are aligned on 128 bit boundaries. All APIC registers are accessed using 32 bit loads
and stores. This implies that to modify a field (e.g., bit, byte) in any register, the whole 32 bit register must be
read, the field modified, and the 32 bits written back. In addition, registers that are described as 64 bits wide are
accessed as multiple independent 32 bit registers.
Table 1. Memory Mapped Registers For Accessing IOAPIC Registers
Memory Address
Mnemonic
Register Name
Access
D/I# SIgnal
FEC0 xy00h
IOREGSEL
I/O Register Select (index)
R/W
0
FEC0 xy10h
IOWIN
I/O Window (data)
R/W
1
NOTES:
xy are determined by the x and y fields in the APIC Base Address Relocation Register located in the PIIX3. Range for x = 0-Fh
and the range for y = 0,4,8,Ch.
Table 2. IOAPIC Registers
Address Offset
Mnemonic
Register Name
Access
00h
IOAPICID
IOAPIC ID
R/W
01h
IOAPICVER
IOAPIC Version
RO
02h
IOAPICARB
IOAPIC Arbitration ID
RO
10−3Fh
IOREDTBL[0:23] Redirection Table (Entries 0-23) (64 bits each)
NOTES:
Address Offset is determined by I/O Register Select Bits [7:0].
R/W
8
PRELIMINARY