82093AA Datasheet, PDF (2/20 Pages) Intel Corporation – I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

82093AA (IOAPIC)
E
CONTENTS
PAGE
1.0. OVERVIEW ......................................................................................................................................................3
2.0. SIGNAL DESCRIPTION ..................................................................................................................................5
2.1. System Bus Signals......................................................................................................................................5
2.2. Clock and Reset Signals...............................................................................................................................6
2.3. APIC Bus Interface .......................................................................................................................................6
2.4. Interrupt Signals ............................................................................................................................................6
2.5. Test and Power Signals ................................................................................................................................7
3.0. REGISTER DESCRIPTION .............................................................................................................................8
3.1. Memory Mapped Registers for Accessing IOAPIC Registers......................................................................9
3.1.1. IOREGSEL—I/O REGISTER SELECT REGISTER .............................................................................9
3.1.2. IOWIN—I/O WINDOW REGISTER.......................................................................................................9
3.2. IOAPIC Registers .........................................................................................................................................9
3.2.1. IOAPICID—IOAPIC IDENTIFICATION REGISTER .............................................................................9
3.2.2. IOAPICVER—IOAPIC VERSION REGISTER....................................................................................10
3.2.3. IOAPICARB—IOAPIC ARBITRATION REGISTER............................................................................10
3.2.4. IOREDTBL[23:0]—I/O REDIRECTION TABLE REGISTERS ............................................................11
4.0. FUNCTIONAL DESCRIPTION ......................................................................................................................14
4.1. INTIN23/SMI# and SMIOUT# Functionality................................................................................................14
5.0. PINOUT AND PACKAGE SPECIFICATIONS ..............................................................................................15
5.1. Pinout Specifications...................................................................................................................................15
5.2. Package Specifications...............................................................................................................................17
6.0. TESTABILITY.................................................................................................................................................18
6.1. Tri-State Of All Output Pins.........................................................................................................................18
6.2. Drive 1’s to all the output pins.....................................................................................................................18
6.3. Drive 0’s to all the output pins.....................................................................................................................19
6.4. NAND Tree .................................................................................................................................................19
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PRELIMINARY