82093AA Datasheet, PDF (12/20 Pages) Intel Corporation – I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

82093AA (IOAPIC)
E
Bit
Description
16
Interrupt Mask—R/W. When this bit is 1, the interrupt signal is masked. Edge-sensitive
interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending).
Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no
side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by
a local APIC has no effect on that interrupt. This behavior is identical to the case where the
device withdraws the interrupt before that interrupt is posted to the processor. It is software's
responsibility to handle the case where the mask bit is set after the interrupt message has been
accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this
bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked
results in the delivery of the interrupt to the destination.
15
Trigger Mode—R/W. The trigger mode field indicates the type of signal on the interrupt pin that
triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.
14
Remote IRR—RO. This bit is used for level triggered interrupts. Its meaning is undefined for
edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s)
accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI
message with a matching interrupt vector is received from a local APIC.
13
Interrupt Input Pin Polarity (INTPOL)—R/W. This bit specifies the polarity of the interrupt
signal. 0=High active, 1=Low active.
12
Delivery Status (DELIVS)—RO. The Delivery Status bit contains the current status of the
delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit
word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send
Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC
bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).
11
Destination Mode (DESTMOD)—R/W. This field determines the interpretation of the
Destination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.
Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical
mode), destinations are identified by matching on the logical destination under the control of the
Destination Format Register and Logical Destination Register in each Local APIC.
Destination Mode IOREDTBLx[11]
Logical Destination Address
0, Physical Mode
1, Logical Mode
IOREDTBLx[59:56] = APIC ID
IOREDTBLx[63:56] = Set of processors
12
PRELIMINARY