82093AA Datasheet, PDF (11/20 Pages) Intel Corporation – I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

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82093AA (IOAPIC)
3.2.4. IOREDTBL[23:0]—I/O REDIRECTION TABLE REGISTERS
Address Offset:
Default Value:
Attribute:
10−11h (IOREDTBL0)
12−13h (IOREDTBL1)
14−15h (IOREDTBL2)
16−17h (IOREDTBL3)
18−19h (IOREDTBL4)
1A−1Bh (IOREDTBL5)
1C−1Dh (IOREDTBL6)
1E−1Fh (IOREDTBL7)
20−21h (IOREDTBL8)
22−23h (IOREDTBL9)
24−25h (IOREDTBL10)
26−27h (IOREDTBL11)
xxx1 xxxx xxxx xxxxh
Read/Write
28−29h (IOREDTBL12)
2A−2Bh (IOREDTBL13)
2C−2Dh (IOREDTBL14)
2E−2Fh (IOREDTBL15)
30−31h (IOREDTBL16)
32−33Fh (IOREDTBL17)
34−35h (IOREDTBL18)
36−37h (IOREDTBL19)
38−39h (IOREDTBL20)
3A−3Bh (IOREDTBL21)
3C−3Dh (IOREDTBL22)
3E−3Fh (IOREDTBL23)
There are 24 I/O Redirection Table entry registers. Each register is a dedicated entry for each interrupt input
signal. Unlike IRQ pins of the 8259A, the notion of interrupt priority is completely unrelated to the position of the
physical interrupt input signal on the APIC. Instead, software determines the vector (and therefore the priority)
for each corresponding interrupt input signal. For each interrupt signal, the operating system can also specify the
signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the
destination and delivery mode of the interrupt. The information in the redirection table is used to translate the
corresponding interrupt pin information into an inter-APIC message.
The IOAPIC responds to an edge triggered interrupt as long as the interrupt is wider than one CLK cycle. The
interrupt input is asynchronous; thus, setup and hold times need to be guaranteed for at lease one rising edge of
the CLK input. Once the interrupt is detected, a delivery status bit internal to the IOAPIC is set. A new edge on
that Interrupt input pin will not be recongnized until the IOAPIC Unit broadcasts the corresponding message over
the APIC bus and the message has been accepted by the destination(s) specified in the destination field. That
new edge only results in a new invocation of the handler if its acceptance by the destination APIC causes the
Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt wasn't already pending at the
destination.)
Bit
63:56
55:17
Description
Destination Field—R/W. If the Destination Mode of this entry is Physical Mode (bit 11=0), bits
[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field
potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical
destination address.
Destination Mode IOREDTBLx[11]
Logical Destination Address
0, Physical Mode
1, Logical Mode
IOREDTBLx[59:56] = APIC ID
IOREDTBLx[63:56] = Set of processors
Reserved.
PRELIMINARY
11