82093AA Datasheet, PDF (6/20 Pages) Intel Corporation – I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

82093AA (IOAPIC)
E
Signal Name
APICREQ#
APICACK1#
APICACK2#
Type
O
I
I
Description
APIC REQUEST: APICREQ# is asserted prior to the APIC sending an
interrupt message over the APIC data bus. This is the request part of a
handshake that insures system level buffer coherency prior to sending an
interrupt over the APIC bus. This signal is tri-stated during reset. This signal
has an internal pull-up resistor.
APIC ACKNOWLEDGE 1: This signal is the acknowledge part of the
handshake indicating that the APIC can send the interrupt message over the
APIC bus. This signal is typically connected to the PIIX3.
APIC ACKNOWLEDGE 2: This signal is the second half of the acknowledge
handshake indicating that the APIC can send the interrupt message over the
APIC bus. This signal is typically connected to the host-to-PCI bridge and
along with APICREQ# and APICACK1# makes up the complete buffer
coherency protocol cycles. If the system does not have a host-to-PCI bridge,
this signal can be tied low.
2.2. Clock and Reset Signals
Signal Name Type
Description
PCICLK
I
PCI CLOCK: This signal is used to synchronize and strobe the data buffer
status signals (APICREQ#, APICACK1#, and APICACK2#). This signal is
typically connect to the PCI clock.
RESET
I
RESET: RESET initializes the IOAPIC’s internal logic and sets the register bits
to their default value.
2.3. APIC Bus Interface
Signal Name Type
Description
APICD[1:0]
I/OD
APIC DATA: These signals are used to send and receive data over the APIC
bus. These signals are tri-stated during reset and must be pulled up to the
appropriate VCC levels of the CPU.
APICCLK
I
APIC CLOCK: The input signal is used to determine when valid data is being
sent over the APIC bus.
2.4. Interrupt Signals
Signal Name Type
Description
INTIN0
ST
Interrupt Input 0: This signal is connected to the redirection table entry 0.
Typically, this signal may be connected to the INTR on the PIIX3 to
communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and
IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of
the system.
INTIN1
ST
Interrupt Input 1: INTIN1 is connected to the redirection table entry 1.
Typically, this signal will be connected to the keyboard interrupt (IRQ1).
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PRELIMINARY