82546EB Datasheet, PDF (7/47 Pages) Intel Corporation – Dual Port Gigabit Ethernet Controller

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Networking Silicon — 82546EB
Introduction
The Intel^® 82546EB Dual Port Gigabit Ethernet Controller is a single, compact component with
two full integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)
functions. The Intel^® 82546EB enables dual port Gigabit Ethernet implementations in a very small
area and can be used for desktop and workstation PC network designs with critical space
constraints.
The Intel^® 82546EB integrates Intel’s fourth generation gigabit MAC and PHY to provide a
standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T
applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving
two channels of data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition, it provides a 64-bit
wide direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant interface
capable of operating at frequencies up to 133 MHz. The 82546EB also delivers a dual port PCI-X
solution without added bridge latency.
The Intel^® 82546EB on-board System Management Bus (SMB) port enables network
manageability implementations required by information technology personnel for remote control
and alerting through the LAN. Using the SMB, management packets can be routed to or from a
management processor. The SMB port enables industry standards, such as Intelligent Platform
Management Interface (IPMI) and Alert Standard Format (ASF), to be implemented using the
82546EB. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities
with standardized interfaces.
The 82546EB Dual Port Gigabit Ethernet Controller architecture is designed to deliver high
performance and PCI/PCI-X bus efficiency. Wide internal data paths eliminate performance
bottlenecks by efficiently handling large address and data words. Combining a parallel and pipe-
lined logic architecture optimized for Gigabit Ethernet and independent transmit and receive
queues, the 82546EB controller efficiently handles packets with minimum latency. The 82546EB
controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface
that maximizes the use of bursts for efficient bus usage. The 82546EB is able to cache up to 64
packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 Kbyte on-chip
packet buffer maintains superior performance as available PCI bandwidth changes. By using
hardware acceleration, the controller is able to offload tasks, such as checksum calculations and
TCP segmentation, from the host processor.
Datasheet
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