82546EB Datasheet, PDF (30/47 Pages) Intel Corporation – Dual Port Gigabit Ethernet Controller

82546EB — Networking Silicon
Table 13. PCI/PCI-X Bus Interface Timing Parameters
Symbol
Parameter
TSU
TSU
(ptp)
TH
TRRSU
TRRH
Input setup time to CLK:
bussed signals
Input setup time to CLK:
point-to-point signals
Input hold time from CLK
REQ64# to RST# setup
time
RST# to REQ64# hold
time
PCI-X 133
MHz
Min Max
1.2
1.2
0.5
10*
TCYC
0
PCI-X 66 MHz PCI 66MHz
Min Max Min Max
1.7
3
1.7
0.5
10*
TCYC
0
5
0
10*
TCYC
0
PCI 33 MHz
Min Max
7
10,
12
0
10*
TCYC
0
Units
ns
ns
ns
ns
ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Table 13. PCI Bus Interface Timing Measurement Conditions
Symbol
VTH
VTL
VTEST
Parameter
Input measurement test voltage (high)
Input measurement test voltage (low)
Output measurement test voltage
Input signal slew rate
PCI-X
0.6*VCC
0.25*VCC
0.4*VCC
1.5
PCI 66 MHz
3.3 v
0.6*VCC
0.2*VCC
0.4*VCC
1.5
Unit
V
V
V
V/ns
Figure 4. PCI Bus Interface Output Timing Measurement
VTH
PCI_CLK
VTEST
VTL
Output
Delay
Tri-State
Output
output current ≤ leakage current
VTEST
VSTEP (3.3V Signalling)
TON
TOFF
24
Datasheet