82546EB Datasheet, PDF (29/47 Pages) Intel Corporation – Dual Port Gigabit Ethernet Controller

Networking Silicon — 82546EB
4.6
Timing Specifications
4.6.1
4.6.1.1
PCI/PCI-X Bus Interface
PCI/PCI-X Bus Interface Clock
Table 12. PCI/PCI-X Bus Interface Clock Parameters
Symbol
Parameter^a
PCI-X 133
MHz
PCI-X 66 MHz PCI 66MHz
Min Max Min Max Min Max
PCI 33 MHz
Min Max
Units
TCYC
TH
TL
CLK cycle time
CLK high time
CLK low time
CLK slew rate
RST# slew rate^b
7.5 20
15
20
15
30
30
3
6
6
11
3
6
6
11
1.5
4
1.5
4
1.5
4
1
50
50
50
50
ns
ns
ns
4
V/ns
mV/ns
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise
cannot render a monotonic signal to appear bouncing in the switching range.
Figure 3. PCI/PCI-X Clock Timing
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Th
0.6 Vcc
Tcyc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
4.6.1.2
PCI/PCI-X Bus Interface Timing
Table 13. PCI/PCI-X Bus Interface Timing Parameters
Symbol
Parameter
TVAL
TVAL
(ptp)
TON
TOFF
CLK to signal valid delay:
bussed signals
CLK to signal valid delay:
point-to-point signals
Float to active delay
Active to float delay
PCI-X 133
MHz
PCI-X 66 MHz PCI 66MHz
Min Max Min Max Min Max
0.7 3.8 0.7 3.8
2
6
0.7 3.8 0.7 3.8
2
6
0
0
2
7
7
14
PCI 33 MHz
Min Max
Units
2
11
ns
2
12
ns
2
ns
28
ns
Datasheet
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