82546EB Datasheet, PDF (16/47 Pages) Intel Corporation – Dual Port Gigabit Ethernet Controller

82546EB — Networking Silicon
3.2.2
3.2.3
3.2.4
Arbitration Signals
Symbol
REQ64#
ACK64#
REQ#
GNT#
LOCK#
Type
Name and Function
Request Transfer. The Request Transfer signal is generated by the current initiator
TS indicating its desire to perform a 64-bit transfer. REQ64# has the same timing as the
Frame signal.
Acknowledge Transfer. The Acknowledge Transfer signal is generated by the currently
TS addressed target in response to the REQ64# assertion by the initiator. ACK64# has the
same timing as the Device Select signal.
TS
Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
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Grant Bus. The Grant Bus signal notifies the 82546EB that bus access has been
granted. This is a point-to-point signal.
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
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target memory device during two or more separate transfers. The 82546EB device
does not implement bus locking.
Interrupt Signals
Symbol
INTA#
INTB#
Type
Name and Function
TS
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the. It is an active
low, level-triggered interrupt signal.
TS
Interrupt B. Interrupt B is used to request an interrupt by port 2 of the 82546EB. It is an
active low, level-triggered interrupt signal.
System Signals
Symbol
CLK
M66EN
RST#
LAN_
PWR_
GOOD
Type
Name and Function
PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and
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is an input to the 82546EB device. All other PCI signals, except the Interrupt A
(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other
timing parameters are defined with respect to this edge.
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PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
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The PME# context is preserved, depending on power management settings.
Most of the internal state of the 82546EB is reset on the de-assertion (rising edge) of
RST#.
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable
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power is available for the 82546EB. When the signal is low, the 82546EB holds itself in
reset state and floats all PCI signals.
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Datasheet