251748-007 Datasheet, PDF (37/102 Pages) Intel Corporation – Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package

Electrical Specifications
Figure 14. Power Up Sequence
BCLK
Vcc
PWRGOOD
RESET#
Tc
Td
VCCVID
VID_GOOD
Ta
Tb
VID[4:0]
Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width)
Td= T36 (PWRGOOD to RESET# de-assertion time)
NOTE: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage
regulator control silicon. For more information on implementation refer to the Processor Platform Design
Guide.
Figure 15. Power Down Sequence
Vcc
PWRGOOD
VCCVID
VID_GOOD
VID[4:0]
NOTES:
1. This timing diagram is not intended to show specific times. Instead a general ordering of events with respect
to time should be observed.
2. When VCCVID is less than 1V, VID_GOOD must be low.
3. Vcc must be disabled before VID[4:0] becomes invalid.
Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage
regulator control silicon. For more information on implementation refer to the Processor Platform
Design Guide.
Intel^® Celeron^® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
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