251748-007 Datasheet, PDF (18/102 Pages) Intel Corporation – Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package

Electrical Specifications
2.5
Reserved, Unused Pins, and TESTHI[12:0]
All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any
other signal (including each other) can result in component malfunction or incompatibility with
future processors. See Chapter 5 for a processor pin listing, and the location of all RESERVED
pins.
For reliable operation, always connect unused inputs or bidirectional signals that are not terminated
on the die to an appropriate signal level. Note that on-die termination has been included on the
Celeron processor on 0.13 micron process to allow signals to be terminated within the processor
silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die
termination. Unused active high inputs should be connected through a resistor to ground (VSS).
Refer to the appropriate platform design guide in Table 1 for the appropriate resistor values.
Unused outputs can be left unconnected. However, this may interfere with some TAP functions,
may complicate debug probing, and may prevent boundary scan testing. A resistor must be used
when tying bidirectional signals to power or ground. When tying any signal to power or ground, a
resistor will allow for system testability. For unused AGTL+ input or I/O signals that do not have
on-die termination, use pull-up resistors of the same value in place of the on-die termination
resistors (R_TT). See Table 15.
The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs can
be terminated on the system board or can be left unconnected. Signal termination for these signal
types is discussed in the appropriate Platform Design Guide listed in Table 1, and the
ITP700 Debug Port Design Guide.
The TESTHI pins should be tied to the processor VCC using a matched resistor with a resistance
value within ± 20% of the impedance of the board transmission line traces. For example, if the
trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required.
The TESTHI pins may use individual pull-up resistors, or may be grouped together as follows. A
matched resistor should be used for each group:
1. TESTHI[1:0]
2. TESTHI[5:2]
3. TESTHI[10:8]
4. TESTHI[12:11]
Additionally, if the ITPCLKOUT[1:0] pins are not used (refer to Section 5.2), they can be
connected individually to VCC using matched resistors, or can be grouped with TESTHI[5:2] with
a single matched resistor. If they are being used, individual termination with 1 kΩ resistors is
required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will
prevent use of debug interposers. This implementation is strongly discouraged for system boards
that do not implement an inboard debug port.
As an alternative, group2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to
the processor VCC. This has no impact on system functionality. TESTHI[0] and TESTHI[12] may
also be tied directly to the processor VCC if resistor termination is a problem, but matched resistor
termination is recommended. In the case of the ITPCLKOUT[1:0] pins, a direct tie to VCC is
strongly discouraged for system boards that do not implement an onboard debug port.
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Intel^® Celeron^® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet