251748-007 Datasheet, PDF (35/102 Pages) Intel Corporation – Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package

Electrical Specifications
Figure 11. System Bus Reset and Configuration Timings
BCLK
Reset
Configuration
A[31:3], SMI#,
INIT#
Configuration
BR0#
Tt
Tv
Tw
Valid
Ty
Tx
Valid
Tv = T13 (RESET# pulse width)
Tw = T45 (Reset configuration signals setup time)
Tx = T46 (Reset configuration signals A[31:3], SMI#, and INIT# hold time)
Ty = T47 (Reset configuration signal BR0# hold time)
Figure 12. Source Synchronous 2X (Address) Timings
T1
T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
T_P
ADSTB# (@ driver)
T_R
T_H
T_J
T_H
T_J
A# (@ driver)
valid
valid
T_S
ADSTB# (@ receiver)
A# (@ receiver)
T_K
valid
valid
T_N
T_M
T_H = T23: Source Sync. Address Output Valid Before Address Strobe
T_J = T24: Source Sync. Address Output Valid After Address Strobe
T_K = T27: Source Sync. Input Setup to BCLK
T_M = T26: Source Sync. Input Hold Time
T_N = T25: Source Sync. Input Setup Time
T_P = T28: First Address Strobe to Second Address Strobe
T_S = T20: Source Sync. Output Valid Delay
T_R = T31: Address Strobe Output Valid Delay
Intel^® Celeron^® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
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