82C55A Datasheet, PDF (20/23 Pages) Intel Corporation – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

82C55A
OTHER TIMINGS
Symbol
Parameter
t_WB
t_lR
t_HR
t_AK
t_ST
t_PS
t_PH
t_AD
t_KD
t_WOB
t_AOB
t_SIB
t_RIB
t_RIT
t_SIT
t_AIT
t_WIT
t_RES
WR ^e 1 to Output
Peripheral Data Before RD
Peripheral Data After RD
ACK Pulse Width
STB Pulse Width
Per Data Before STB High
Per Data After STB High
ACK ^e 0 to Output
ACK ^e 1 to Output Float
WR ^e 1 to OBF ^e 0
ACK ^e 0 to OBF ^e 1
STB ^e 0 to IBF ^e 1
RD ^e 1 to IBF ^e 0
RD ^e 0 to INTR ^e 0
STB ^e 1 to INTR ^e 1
ACK ^e 1 to INTR ^e 1
WR ^e 0 to INTR ^e 0
Reset Pulse Width
82C55A-2
Min
Max
350
0
0
200
100
20
50
175
20
250
150
150
150
150
200
150
150
200
500
Units
Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
see note 1
see note 2
NOTE
u v 1 INTR may occur as early as WR
2 Pulse width of initial Reset pulse after power on must be at least 50 mSec Subsequent Reset pulses may be 500 ns
minimum The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic ‘‘one’’ level
after the reset pulse
20