82C55A Datasheet, PDF (11/23 Pages) Intel Corporation – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

Input Control Signal Definition
STB (Strobe Input) A ‘‘low’’ on this input loads
data into the input latch
IBF (Input Buffer Full F F)
A ‘‘high’’ on this output indicates that the data has
been loaded into the input latch in essence an ac-
knowledgement IBF is set by STB input being low
and is reset by the rising edge of the RD input
INTR (Interrupt Request)
A ‘‘high’’ on this output can be used to interrupt the
CPU when an input device is requesting service
INTR is set by the STB is a ‘‘one’’ IBF is a ‘‘one’’
and INTE is a ‘‘one’’ It is reset by the falling edge of
RD This procedure allows an input device to re-
quest service from the CPU by simply strobing its
data into the port
INTE A
Controlled by bit set reset of PC₄
INTE B
Controlled by bit set reset of PC₂
82C55A
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Figure 8 MODE 1 Input
Figure 9 MODE 1 (Strobed Input)
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