82C55A Datasheet, PDF (13/23 Pages) Intel Corporation – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

82C55A
Combinations of MODE 1
Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed
I O applications
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Figure 12 Combinations of MODE 1
Operating Modes
MODE 2 (Strobed Bidirectional Bus I O) This
functional configuration provides a means for com-
municating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving
data (bidirectional bus I O) ‘‘Handshaking’’ signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1 Interrupt generation
and enable disable functions are also available
MODE 2 Basic Functional Definitions
 Used in Group A only
 One 8-bit bi-directional bus port (Port A) and a 5-
bit control port (Port C)
 Both inputs and outputs are latched
 The 5-bit control port (Port C) is used for control
and status for the 8-bit bi-directional bus port
(Port A)
Bidirectional Bus I O Control Signal Definition
INTR (Interrupt Request) A high on this output can
be used to interrupt the CPU for input or output oper-
ations
Output Operations
OBF (Output Buffer Full) The OBF output will go
‘‘low’’ to indicate that the CPU has written data out
to port A
ACK (Acknowledge) A ‘‘low’’ on this input enables
the tri-state output buffer of Port A to send out the
data Otherwise the output buffer will be in the high
impedance state
INTE 1 (The INTE Flip-Flop Associated with
OBF) Controlled by bit set reset of PC₆
Input Operations
STB (Strobe Input) A ‘‘low’’ on this input loads
data into the input latch
IBF (Input Buffer Full F F) A ‘‘high’’ on this output
indicates that data has been loaded into the input
latch
INTE 2 (The INTE Flip-Flop Associated with IBF)
Controlled by bit set reset of PC₄
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