80C196MH Datasheet, PDF (16/41 Pages) Intel Corporation – 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
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Table 7. Signal Descriptions (Continued)
Signal
Name
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
PACT#
PALE#
PBUS.15:8
PBUS.7:0
PMODE.3
PMODE.2
PMODE.1
PMODE.0
PROG#
PVER
PWM1:0
RD#
Type
Description
Multiplexed
With
O Port 6. This is an 8-bit output port that is multiplexed with the PWM1
special functions of the waveform generator and PWM
PWM0
peripherals. The WG_OUT register configures the pins,
WG3
establishes the output polarity, and controls whether changes WG3#
to the outputs are synchronized with an event or take effect WG2
immediately.
WG2#
WG1
WG1#
O Programming Active. In auto-programming mode, PACT# P2.5/COMP1
low indicates that programming activity is occurring.
I Programming ALE. In slave programming mode, this active- P2.1/SCLK0#/BCLK0
low input indicates that ports 3 and 4 contain a
command/address. When PALE# is asserted, data and
commands on ports 3 and 4 are read into the device.
I/O Programming Bus. In programming modes, used as a
P4.7:0/AD15:8
bidirectional port with open-drain outputs to pass commands, P3.7:0/AD7:0
addresses, and data to or from the device. Used as a regular
system bus to access external memory during auto-
programming mode. When using slave programming mode,
the PBUS is used in open-drain I/O port mode (not as a
system bus). In slave programming mode, you must add
external pull-up resistors to read data from the device during
the dump word routine.
I Programming Mode Select. Determines the OTPROM
P0.7/ACH7/T1DIR
programming algorithm that is to be performed. PMODE is P0.6/ACH6/T1CLK
sampled after a device reset when EA# = V_EA and must be
stable while the device is operating.
P0.5/ACH5
P0.4/ACH4
I Programming Start. This active-low input is valid only in
P2.2/EPA1
slave programming mode. The rising edge of PROG# latches
data on the PBUS and begins programming. The falling edge
of PROG# ends programming.
O Program Verification. In programming modes, this active-
high output signal is asserted to indicate that the word has
programmed correctly. (PVER low after the rising edge of
PROG# indicates an error.)
P2.0/EPA0
O Pulse Width Modulator Outputs. These are PWM output
pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
P6.7:6
O Read. Read-signal output to external memory. RD# is
asserted only during external memory reads.
P5.3
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