IA6805E2 Datasheet, PDF (9/31 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
I(Interrupt Mask Bit)
The interrupt mask bit indicates that both the external interrupt and the timer interrupt are
disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is
processed as soon as the interrupt bit is cleared.
H(Half Carry Bit)
The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an
ADD or ADC operation.
Resets:
The MPU can be reset by initial power up or by the external reset pin (reset_n).
POR(Power On Reset)
Power on reset occurs on initial power up. It is strictly for power initialization conditions
and should not be used to detect drops in the power supply voltage. There is a 1920 t_CYC
time out delay from the time the oscillator is detected. If the reset_n pin is still low at the
end of the delay, the MPU will remain in the reset state until the external pin goes high.
Reset_n
The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of t_cyc
to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise
immunity capability.
Interrupts:
The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer
interrupt request, or the software interrupt instruction. When any of these interrupts occur,
normal processing is suspended at the end of the current instruction execution. The
processor registers are saved on the stack (stacking order shown in Figure 7) and the
interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after
the RTI instruction causes the register contents to be recovered from the stack. When the
current instruction is completed, the processor checks all pending hardware interrupts and if
unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. Masked interrupts are latched for later interrupt service. External
interrupts hold higher priority than timer interrupts. At the end of an instruction execution,
if both an external interrupt and timer interrupt are pending, the external interrupt is
serviced first. The SWI gets executed with the same priority as any other instruction if the
hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing
flowchart.
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