IA6805E2 Datasheet, PDF (14/31 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Wait Mode:
The wait instruction places the MPU in low power consumption mode. The wait instruction
disables clocking of most internal registers. The DS and AS output lines go “low” and the
RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The
high order address lines remain at the address of the next instruction. External interrupts are
enabled by clearing the I bit in the condition code register. All other registers, memory, and
I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the
MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait
mode. If an external and a timer interrupt occur at the same time, the external interrupt is
serviced first. Then, if the timer interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is
no longer in the wait mode. Figure 12 shows a flowchart of the wait function.
WAIT
OSCILLATOR
ACTIVE,
CLEAR I BIT,
TIMER CLOCK
ACTIVE,
RESET?
N
Y
EXTERNAL
N
INTERRUPT?
Y
TIMER
INTERRUPT?
N
(TCR BIT7
= 1)
Y
FETCH EXTERNAL
INTERRUPT, RESET,
OR TIMER
INTERRUPT (FROM
WAIT MODE ONLY)
TCR
N
BIT 6 = 0?
Y
Figure 12. WAIT Function Flowchart
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