IA6805E2 Datasheet, PDF (3/31 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
SIGNAL NAME
V D D and V SS
(Power and Ground)
RESET_n
(Reset)
IRQ_n
(Interrupt Request)
LI
(Load Instruction)
I/O
N/A
I
I
O
DESCRIPTION
Source: These two pins provide power to the chip. V _{D D} provides + 5 volts (±0.5) power
and V _SS is ground.
T T L : I n p u t pin that c a n b e used t o reset the M P U ' s i n t e r n a l state b y p u l l i n g the reset_n
pin low.
T T L : I n p u t pin t h a t is level a n d e d g e sensitive. Can b e u s e d t o r e q u e s t a n i n t e r r u p t
sequence.
T T L w i t h s l e w r a t e c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t a n e x t o p c o d e f e t c h i s in
p r o g r e s s . U s e d o n l y f o r c e r t a i n d e b u g g i n g a n d t e s t s y s t e m s . N o t c o n n e c t e d in n o r m a l
operation. Overlaps Data Strobe ( D S ) signal. This output is capable of driving o n e
standard TTL load and 50pF.
DS
(Data Strobe)
RW_n
(Read/Write)
AS
(Address Strobe)
PA0-PA7/PB0-PB7
(Input/Output Lines)
A8-A12
(High Order Address Lines)
B0-B7
(Address/Data Bus)
Timer
OSC1, OSC2
(System Clock)
O
O
O
I/O
O
I/O
I
T T L with s l e w rate control: O u t p u t pin u s e d to transfer data t o o r from a p e r i p h e r a l o r
memory. D S occurs anytime the M P U does a data read or write and during data transfer
t o o r f r o m i n t e r n a l m e m o r y . D S is a v a i l a b l e a t f _{O S C} ÷ 5 w h e n t h e M P U is n o t in t h e W A I T
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
T T L w i t h s l e w rate c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h e d i r e c t i o n o f d a t a transfer
from internal memory, I/O registers, and external peripheral devices and memories.
I n d i c a t e s t o a selected p e r i p h e r a l w h e t h e r t h e M P U is to r e a d ( R W _ n high) o r w r i t e
( R W _ n l o w ) data o n t h e next data strobe. This output is capable of driving o n e standard
TTL load and 130pF.
T T L with s l e w rate c o n t r o l : O u t p u t strobe u s e d to indicate the p r e s e n c e o f a n address
o n the 8-bit multiplexed bus. T h e A S l i n e is u s e d to demultiplex the eight least significant
address bits from the data bus. A S is available at f_OSC ÷ 5 w h e n the M P U is not in the
W A I T o r S T O P modes. This output is capable of driving one standard T T L load and
130pF.
T T L with slew rate control: These 1 6 lines constitute I n p u t / O u t p u t ports A and B .
E a c h l i n e is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r a n i n p u t o r o u t p u t u n d e r s o f t w a r e
control of the Data Direction Register ( D D R ) a s s h o w n below in Table 1 and Figure 2 .
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t i n t h e D D R to a " 1 " f o r
o u t p u t and a " 0 " f o r input. In the output m o d e the bits are latched a n d appear o n the
c o r r e s p o n d i n g output pins. All t h e D D R ' s are initialized to a " 0 " o n reset. T h e o u t p u t
port registers are n o t initialized on reset. Each output is capable of driving one standard
TTL load and 50pF.
T T L with slew rate control: These five outputs constitute the higher order non-
multiplexed address lines. E a c h output is capable of driving o n e standard T T L load and
130pF.
T T L with slew rate control: These bi-directional lines constitute the lower order
addresses and data. These lines are multiplexed with address present at address strobe
t i m e and data present at data strobe time. W h e n in the data m o d e , these lines are bi-
directional, transferring data to and from memory and peripheral devices as indicated by
the R W _ n pin. A s outputs, these lines are capable of driving o n e standard T T L load and
130pF.
T T L : Input used to control the internal timer/counter circuitry.
T T L Oscillator input/output: These pins provide control input for the on-chip clock
oscillator circuits. Either a crystal o r external clock is c o n n e c t e d to these p i n s to provide
a system clock. T h e c r y s t a l c o n n e c t i o n is s h o w n in F i g u r e 3 . T h e O S C 1 to b u s
transitions for system designs using oscillators slower than 5MHz is shown in Figure 4 .
Crystal
External Clock
I/O
T h e c i r c u i t s h o w n i n F i g u r e 3 is r e c o m m e n d e d w h e n u s i n g a c r y s t a l . A n e x t e r n a l C M O S
o s c i l l a t o r is r e c o m m e n d e d w h e n u s i n g c r y s t a l s o u t s i d e t h e s p e c i f i e d r a n g e s . T o m i n i m i z e
output distortion and start-up stabilization time, the crystal and components should be
mounted as close to the input pins as possible.
W h e n a n external clock is u s e d , it should b e a p p l i e d to t h e O S C 1 i n p u t w i t h the O S C 2
input not connected, as shown in Figure 3 .
Table 1
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