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IA64250 Datasheet, PDF (6/21 Pages) InnovASIC, Inc – Histogram/Hough Transform Processor
IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
INITIALIZATION MODE:
Initialization defines the operation of the IA64250. The mode and marker memories store
66 nine-bit words that define the operation of the part and contain marker information. The
REGADR input is used to select the proper register. Data is written over the CI bus and
read on the DO bus. The AT pin controls whether data is a mode word or a marker. When
AT is low, the data written is mode information, which is stored in the mode registers
contained in the controller block. When AT is high, the data is a marker, and is stored in the
marker memory. To prevent erroneous operation STARTIOn should be high, and IODV
and DV should be low during initialization.
Mode Register Table:
A REGA R/ BIT LOCATION
T DR
W
W ci0
ci1
ci2
ci3
ci4
ci5
ci6
ci7
ci8
R do0 do1 do2
do3 do4 do5
do6
do7
do8
00
W sel0 sel1 sel2
sel3 lut0 lut1
sh1
sat
TESTn
01
W fn0 fn1 Eq
io0 io1 hclr0
hclr1
func pdwn
Marker Memory Table:
AT REGADR
10
11
12
13
R/W
R
R
R
R
CONTENTS
GREY LEVEL OF MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 9-17
MAXIMUM ACC COUNT BITS 18-23*
1 16
1 17
1 18
1 19
W
TEST MODE, DO NOT ACCESS
W
TEST MODE, DO NOT ACCESS
W
TEST MODE, DO NOT ACCESS
W
TEST MODE, DO NOT ACCESS
1 32
1 33
1 34
1 35
R/W
R/W
R/W
R/W
R/W MARKER 0 GREY LEVEL BITS 0-8
R/W MARKER 0 ACC COUNT BITS 0-8
R/W MARKER 0 ACC COUNT BITS 9-17
R/W MARKER 0 ACC COUNT BITS 18-23*
1 36
R/W
R/W MARKER 1 GREY LEVEL BITS 0-8
1 37
R/W
R/W MARKER 1 ACC COUNT BITS 0-8
1 38
R/W
R/W MARKER 1 ACC COUNT BITS 9-17
1 39
R/W
R/W MARKER 1 ACC COUNT BITS 18-23*
.
.
.
1 56
R/W
R/W MARKER 6 GREY LEVEL BITS 0-8
1 57
R/W
R/W MARKER 6 ACC COUNT BITS 0-8
1 58
R/W
R/W MARKER 6 ACC COUNT BITS 9-17
1 59
R/W
R/W MARKER 6 ACC COUNT BITS 18-23*
*ACC COUNT BIT 18-23 APPEARS ON BIT LOCATION 0-5 RESPECTIVELY
Copyright © 2000
innovASIC

The End of Obsolescence™
ENG211001219-01
Page 6 of 21
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