IA64250 Datasheet, PDF (12/21 Pages) InnovASIC, Inc – Histogram/Hough Transform Processor

IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
coordinates are stored in the ACC RAM. Storage space is assigned sequentially as defined by
the FP counter.
I/O Mode:
Once a computation has taken place, the user reads data from the LUT or the ACC RAM.
These operations typically take place during a vertical retrace or some other period when the
processor is not busy and AT is low. This mode is also to load the LUT with the desired
transfer function. Generally, these operations are controlled by CLK2 so that data may be
read or written at a different rate than the pixel clock. If the ACC RAM is accessed, the
marker values will be updated.
The internal signals hclr(1:0) control whether or not the ACC RAM is cleared during I/O
operations. These values are stored in the mode registers of the controller block during the
initialization mode. If both hclr0 and hclr1 are high then the ACC RAM will not be cleared
during any I/O operation. If hclr0 is high and hclr1 is low, then each ACC RAM location
will be cleared after it is read. If both hclr0 and hclr1 are low then each ACC RAM location
is cleared when either the ACC RAM location or the corresponding LUT RAM location is
accessed.
Read/Transfer ACC RAM:
Once the histogram has been computed and stored in the ACC RAM, the user asserts
STARTIOn low to initiate reading of the data. One data value is read out of the ACC RAM
during each clock cycle of CLK2 starting with address 0. The address counter for the ACC
RAM is contained in the controller block. If STARTIO remains low, all 512 data values will
be read in sequential address order and the processor will return to pixel processing mode
after 512 clock cycles. If STARTIOn is returned high, the I/O mode halts and the user can
return to pixel processing operations. When the output flag IODV is high, the processor
has placed valid data from the LUT or ACC RAMs onto the I/O bus.
The user controls the destination of the ACC RAM data via the io(1:0) bits in the mode
registers located in the control memory. Code 01 signifies that histogram data will be placed
on the DO output bus, while code 00 will transfer data from the ACC RAM to the LUT
RAM.
In both cases the user can modify the histogram data. By setting the internal EQ control bit
high, an accumulated histogram will be output. The shifter allows the user to determine
which nine bits of the 24 bit ACC RAM output will be directed to the DO bus and LUT
RAM. The shifter control data is stored in the mode registers. The control signals for the
shifter are generated in the controller block. Additional control over the output format can
be obtained via the SAT pin in the control memory. When SAT is high, the resultant nine
bit shifted output will be forced to 511 (111111111) if overflow occurs in the shifter.
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