IA64250 Datasheet, PDF (10/21 Pages) InnovASIC, Inc – Histogram/Hough Transform Processor

IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
LUT RAM Hough Transform Mode
(45 < φ ≤ 90):
Address
0
1
.
.
.
.
511
Memory Contents
0*cot φ
1*cot φ
.
.
.
.
511*cot φ
LUT RAM Find Pixel Mode:
Address
0
1
.
.
.
.
511
Memory Contents
0-5
6-7
Flag for Grey Value t0
0
Flag for Grey Value t1
1
.
Tag
.
Bit
.
.
Flag for Grey Value t511
511
8
Not Used
COMPUTATION MODE:
Histogram Computation:
During histogram computation, the ACC RAM and LUT RAM form the active elements of
the data path. The ACC RAM is addressed by the controller block. The ACC RAM address
is the DI input signal. The data addressed by the DI signal is incremented if the DV input
signal is high, otherwise the data is left unchanged. The LUT is not used in the computation
of the histogram and can concurrently modify the image by a user-defined transfer function.
The DI signal addresses the LUT and the LUT data appears on the VDO output pins two
clock cycles later.
Histogram equalization can be performed in real time. The histogram is stored in the ACC
RAM. The equalization transfer function must be computed and transferred into the LUT
RAM. Then during the next frame as a new histogram is being computed, data will also be
equalized in real time and passed to the VDO output pins.
Copyright © 2000
innovASIC

The End of Obsolescence™
ENG211001219-01
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