XC226X_08 Datasheet, PDF (93/116 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2267 / XC2264
XC2000 Family Derivatives
Electrical Parameters
4.6.2 Definition of Internal Timing
The internal operation of the XC226x is controlled by the internal system clock f_SYS.
Because the system clock signal f_SYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate f_SYS. This must be considered when calculating the timing
for the XC226x.
Phase Locked Loop Operation (1:N)
f_IN
f_SYS
Direct Clock Drive (1:1)
f_IN
TCS
f_SYS
Prescaler Operation (N:1)
f_IN
TCS
f_SYS
TCS
M C_XC2X_CLOCKGEN
Figure 18 Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
91
V2.1, 2008-08