XC226X_08 Datasheet, PDF (31/116 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2267 / XC2264
XC2000 Family Derivatives
General Device Information
Table 4
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
99 ESR0
O0 / I St/B External Service Request 0
Note: After power-up, ESR0 operates as open-
drain bidirectional reset with a weak pull-up.
U1C0_DX0E I
St/B USIC1 Channel 0 Shift Data Input
U1C0_DX2B I
St/B USIC1 Channel 0 Shift Control Input
10 V_DDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Table 12
for details.
38, V_DDI1
64,
88
14 V_DDPA
2,
V_DDPB
25,
27,
50,
52,
75,
77,
100
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple with a ceramic capacitor, see Table 12
for details.
All V_DDI1 pins must be connected to each other.
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
V_DDP/V_SS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6, and
P15 are fed from supply voltage V_DDPA.
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
V_DDP/V_SS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage V_DDPB.
1, V_SS
26,
51,
76
-
PS/-- Digital Ground
All V_SS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected to V_SS.
The respective board area must be
connected to ground (if soldered) or left free.
1) To generate the reference clock output for bus timing measurement, f_SYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Data Sheet
29
V2.1, 2008-08