XC226X_08 Datasheet, PDF (33/116 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2267 / XC2264
XC2000 Family Derivatives
Functional Description
3
Functional Description
The architecture of the XC226x combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC226x.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC226x.
PSR A M
16/32/64 Kbytes
Program Flash 0
256 Kbytes
Program Flash 1
192/256 Kbytes
Program Flash 2
0/64/256 Kbytes
System Functions
Clock, Reset, Power Control,
Stand-By RAM
D PR A M
2 Kbytes
D SR A M
16 Kbytes
C PU
C166SV2 - Core
Interrupt & PEC
Interrupt Bus
OCDS
Debug Support
EBC
LXBus Control
External Bus
C o n t ro l
WDT
RTC
ADC1 ADC0
8-Bit/ 8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
GPT
T2
T3
T4
... _{CC2 CCU63 CCU60}
T7 T12
T12
T8 T13
T13
T5
BRTG6en
USIC2 USIC1 USIC0
2 Ch., 2 Ch., 2 Ch.,
64 x 64 x 64 x
Buffer Buffer Buffer
M ulti
CAN
RS232, RS232, RS232,
LIN, LIN, LIN,
SPI, SPI, SPI,
IIC, IIS IIC, IIS IIC, IIS
5 ch.
P1 5
Port 5
5
11
P1 0
16
P7 P6 P4
53 4
P2
P1 P0
13
8
8
Figure 3 Block Diagram
MC_XC226X_BLOCKDIAGRAM
Data Sheet
31
V2.1, 2008-08