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XC226X_08 Datasheet, PDF (44/116 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance | |||
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XC2267 / XC2264
XC2000 Family Derivatives
Functional Description
Table 6
XC226x Interrupt Nodes (contâd)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
USIC2 Cannel 1, Request 0
U2C1_0IC
xxâ017CH
5FH / 95D
USIC2 Cannel 1, Request 1
U2C1_1IC
xxâ0180H
60H / 96D
USIC2 Cannel 1, Request 2
U2C1_2IC
xxâ0184H
61H / 97D
Unassigned node
â
xxâ0188H
62H / 98D
Unassigned node
â
xxâ018CH
63H / 99D
Unassigned node
â
xxâ0190H
64H / 100D
Unassigned node
â
xxâ0194H
65H / 101D
Unassigned node
â
xxâ0198H
66H / 102D
Unassigned node
â
xxâ019CH
67H / 103D
Unassigned node
â
xxâ01A0H
68H / 104D
Unassigned node
â
xxâ01A4H
69H / 105D
Unassigned node
â
xxâ01A8H
6AH / 106D
SCU Request 1
SCU_1IC
xxâ01ACH
6BH / 107D
SCU Request 0
SCU_0IC
xxâ01B0H
6CH / 108D
Program Flash Modules
PFM_IC
xxâ01B4H
6DH / 109D
RTC
RTC_IC
xxâ01B8H
6EH / 110D
End of PEC Subchannel
EOPIC
xxâ01BCH
6FH / 111D
1) Register VECSEG defines the segment where the vector table is located.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting with a distance of 4 (two words) between two vectors.
Data Sheet
42
V2.1, 2008-08
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