V23832-T2131-M101 Datasheet, PDF (9/30 Pages) Infineon Technologies AG – PAROLI 2 Tx AC, 1.6 Gbit/s

V23832-T2131-M101
V23832-R121-M101
Description
Receiver V23832-R121-M101
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, trans impedance amplifiers, and gain amplifiers. There are two different modules
available, one for LVDS and one for CML output. This description only refers to a module
with LVDS output. A module description for Infineon’s adjustable CML output can be
provided separately.
The data rate is up to 1600 Mbit/s for each channel. The receiver module’s min. data rate
of 500 Mbit/s is specified for the CID¹⁾ worst case pattern (disparity 72) or any pattern
with a lower disparity.
Additional Signal Detect outputs (SD1 active high / –SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs
will not be effected.
All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is
at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per
meter for the fiber optic cable.
Optical
Input
12
Data
12
Pin
Diode
Array
Amplifier
Electrical
Output
Gain
12
Amplifier
Signal
Detect
Circuit
LVDS
Output
Stage
12
Data Out
SD1
−SD12
ENSD Output Enable (OEN)
File: 3333
Figure 5 Receiver Block Diagram
1) _{Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,}
ITU-T recommendation G.957 sec. II.
Data Sheet
9
2003-11-19